Although FPGA technology oflers the potential of designing high performance systems at low cost for a wide range of applications, its programming model is prohibitively low level requiring either4 dedicated FPGA-experienced programmer or basics digital design knowledge. To allow a signaUimage processing end-user to benefit from this kind of devices, the level of design abstraction needs to be r...

This paper presents an example of using a hardwaresoftware codesign by implementation of the RSA cipher embedded in Field Programmable Logic Devices (FPLDs). The effect of moving the computationally most expensive parts of RSA into an optimized scalable Montgomery Multiplication (MM) coprocessor is analyzed and compared with a pure software solution.

Reconfigurable coprocessors, most commonly implemented with field programmable gate array (FPGA) technology, have been shown effective in accelerating certain classes of applications. Computation-intense kernels can be selected automatically or by hand for acceleration using the coprocessor. For each kernel selected, aconfiguration must be constructed to implement the computation graph of the k...

In this paper evaluation issues of an FPGA implementation of the feature extraction gradient adaptive lattice (GAL) filter are presented. Two different hardware architectures for implementation in the Virtex family of FPGA devices were proposed, namely a single GAL section coprocessor of Virtex PowerPC, and a pipeline architecture. Both of them show significantly higher performance comparing to...

In exploring the efficacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture enables exploring ...

Todays FPGA technology allows reconngurable hardware to be integrated into standard PC hardware. A hardware like this allows for on-they reconngurable hardware. It is possible to remove and insert complete subsystems just by reinitializing the conngurable components. These systems make new demands on software that often can't be fulllled by the classical device driver concept used in todays ope...

Unsecure computational environments threaten many nancial cryptography implementations, and other sensitive computation. High-performance secure coprocessors can address these threats. However, using this technology for practical security solutions requires overcoming numerous technical and business obstacles. These obstacles motivate building a high-performance secure coprocessor that balances...

W ork leading toward the IBM 4758 started, arguably, in the 1980s when the Abyss project began exploring techniques to build tamper-responsive hardware and use that technology to protect against software piracy. 1,2 Influenced by this earlier work, we sought to build a secure coprocessor, defined as a tamper-responding device derived from the Abyss, Citadel, and 4755 work. We wanted to provide ...

Secure coprocessors enable secure distributed applications by providing safe havens where an application program can execute (and accumulate state), free of observation and interference by an adversary with direct physical access to the device. However, for these coprocessors to be effective, participants in such applications must be able to verify that they are interacting with an authentic pr...

In these last years there have been an increasing need to secure information transmitted on the Internet. In order to meet this requirement in an absolutely secure way, the major OEMs have designed devices that complies with these requirements. Such device embeds very high-level type of technology that make their design, build and development a real big challenge. Our laboratory (of Celestica I...