The construction of an HPSG grammar (Headdriven Phrase Structure Grammar) treating Arabic specificities is not an easy task. In fact, several syntactic phenomena must be taken into account. Thus, the main objective of this work is to construct an Arabic HPSG grammar based on a proposed type hierarchy that categorizes Arabic words. In fact, some adaptations were introduced to HPSG, at the level ...

In this paper, we present a methodology to explore and evaluate the crosstalk noise and the profile of its variations, and the delay of interconnects through investigation of two groups of interconnect structures in nano scale VLSI circuits. The interconnect structures in the first group are considered to be partially coupled identical lines. In this case, by choosing proper values for differen...

T umefactive demyelinating lesion (TDL) is defined as a solitary de myelin ating lesion greater than 2 cm. Mass effect and contrast enhancement on neuroimaging make it difficult to distinguish this type of lesion from high-grade gliomas. Multiple sclerosis (MS) accounts for most cases of TDL. Even in patients with established MS, an atypical manifestation of a large lesion can suggest concurren...

Article history: Received 15 April 2006 Received in revised form 7 August 2008 Accepted 16 August 2008

Rapamycin (RAPA), an inhibitor of cytokine responses, is under investigation in humans for graft-vs-host disease (GVHD) prevention. The mechanisms responsible for GVHD prevention are unknown. We show that RAPA is more effective in inhibiting CD8+ or TCR gammadelta+ than CD4+ T cell-mediated murine GVHD. To determine how RAPA inhibited GVHD, thoracic duct lymphocytes (TDL) were isolated from rec...

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

In this paper, we present a novel approach to comprehensively verify timing sensitive blocks, specifically Delay Lines and Delay Locked Loops by modelling transient behavior into the RTL. This paper focuses on reduction of simulation time and increase in design turnaround time. Information gathered from a small set of spice simulations is modelled into a Verilog based environment, which gives s...

The rapid growth in telecommunication traffic demands a higher-speed asynchronous transfer mode (ATM) switching system. At present, the upper limit of the system clock rate is determined by the maximum clock rate of conventional semiconductor memory devices, such as the register files used in ATM cell buffer storage. This is because the maximum clock rate of these register files is restricted b...