Multipliers play a vital role in many cryptographic applications like elliptic curve cryptography, RSA and other algorithms. The direct truncation of least significant part of the product leads to large error in the resultant product when fixed width output is the requirement. This paper proposes a truncation error minimizing logic which greatly reduces truncation error. Truncation error minimi...

In most approximation techniques for implementing a variable fractional delay, like Lagrange interpolation, the magnitude response varies considerably with the delay. Instead, it would be desirable to keep the magnitude response the same for all delay values. In this paper, we propose a novel method for optimizing the parameters of the least−squared error spline transition band fractional delay...

A low-voltage analog multiplier operating at 1.2V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6μm CMOS technology. Simulation results indicate an IP3 of 4.9dBm and a spur free dynamic ran...

INTRODUCTION Parallel transmission is an emerging technique that has great potential in many applications such as reducing selective RF pulse duration and improving B1 and B0 field inhomogeneity in high fields [1-3]. A potential issue in parallel transmission is elevated RF power deposition which is characterized by the specific absorption ratio (SAR). In parallel excitation, the effect of elec...

This study presents a novel sequential Type-I optimal normal basis multiplier in GF(2) with a regular structure. The proposed multiplier has a slightly higher space complexity than the Reyhani-Masoleh-Hasan’s (RMH) multiplier, but is 27% faster than the RMH multiplier. Furthermore, the proposed multiplier is highly regular, modular, expandable and well-suited to VLSI implementation. A new norma...

In this paper, we investigate the optimality of training signals for linear minimummean square error (LMMSE) channel estimation in multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) with frequency-selective fading channels. This is a very challenging problem due to its mathematical intractability and has not been analytically solved in the literature. Using ...

Barium Strontium Titanate (BST) varactors utilized in a VCO demonstrate unique tuning characteristics compared to junction varactors. A 2.7 GHz microstrip line VCO operates in a tracking phaselock loop configured as an X4 frequency multiplier. BST oscillator tuning and the effect on loop dynamics is observed by the intentional design of an under damped system. Oscillator noise correction and pe...

In this work we present and study bottom-up, or multiplicative, clock synthesis and compare it to a proposed and alternative top-down, or divisive, methodology. The focus of the work is on the short-term stability for each approach and the implications associated with frequency multiplication and division. The analysis and simulation demonstrate that for a common application, a top-down clock s...