We examine the application of High Level Synthesis to FPGA based computing systems. Our experience shows that high level synthesis allows for a level of design space exploration unrealizeable with register transfer level techniques. In addition, the use of high level tools allow designers to prototype their designs with high quality results and fast design turn around times. Our design ow makes...

Information on false paths in a circuit is useful for design and test. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established ...

We present a solution to the veriication problem of high-level synthesis. The high-level synthesis system CALLAS takes as input an algorithmic speciication, in VHDL, and produces as output an EDIF netlist. Both, the speciication and the generated netlist can be interpreted as nite state machine descriptions. Then, in this context, the veriication problem is reduced to proving the behavioral equ...

Emerging design problems are prompting the use of code motion and speculative execution in high-level synthesis to shorten schedules and meet tight timeconstraints. However, some code motions are not worth doing from a worst-case execution perspective. We propose a technique that selects the most promising code motions, thereby increasing the density of optimal solutions in the search space.

An innovative approach for high-level synthesis of digital circuits with semi-concurrent selfchecking abilities is introduced, achieving a compromise between redundancy and checking effectiveness. Attention is mainly focused on the data path, described as a general Sequencing Graph including linear paths as well as loops and branches. A reference architecture is defined; a technique allowing to...

On-line testability is essential in designs with high reliability requirements. High-level synthesis reduces time-to-market and enables efficient design space exploration. In our work, we implement on-line testable designs in a high-level synthesis context. We refer to our new technique (inversion testing) and exploit its features, in an attempt to reduce hardware penalties.

This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated togethe...

This paper proposes to use the techniques of Concatenative Sound Synthesis in the context of real-time Music Interaction. We describe a system that generates an audio track by concatenating audio segments extracted from pre-existing musical files. The track can be controlled in real-time by specifying high-level properties (or constraints) holding on metadata about the audio segments. A constra...