This paper proposes a static test approach suitable for built-in-self-test (BIST) of Analog-to-digital converter Intellectual Property (IP). Static parameters (INL, DNL, gain, offset) are tested without using test equipment. The proposed BIST structure is applicable for testing models of analog-to-digital converters up to 12bits of resolution. Comparison results with dynamic test equipment vali...

IEEE1149.1 Boundary Scan has become an important test technique within complex IC's and boards in today's electronic assemblies, providing a low cost, high fault coverage test methodology for digital designs. The most common approach is for the IEEE1149.1 test to be performed in factory with test vectors being supplied by external test equipment, however new IEEE1149.1 test support devices are ...

Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to t...

A major problem for applying self-test techniques to MEMS is the multi-domain nature of the sensing parts that require special test equipment for stimuli generation. In this work we describe, for three different types of MEMS that work in different energy domains, how the required non-electrical test stimuli can be induced onchip by means of electrical signals. This provides the basis for addin...

For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees c...

Memories are the most dominating blocks present on a chip. All types of chips contain embedded memories such as a Read Only Memory (ROM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and flash memory. Testing of these memories is a very tedious and challenging job as area over head, testing time and cost of the test play an important role. In this work an efficient V...

This paper presents the integration of a proprietary hierarchical and distributed test access mechanism called HDBIST and a BIST insertion commercial tool. The paper briefly describes the architecture and the features of both the environments and it presents some experimental results obtained on an industrial SoC. 1. The HDBIST architecture HDBIST (Hierarchical-Distributed-Data BIST) is a propr...

Built-in self-test (BIST) refers to those testing techniques where additional hardware is added to a design so that testing is accomplished without the aid of external hardware. Usually, a pseudo-random generator is used to apply test vectors to the circuit under test and a data compactor is used to produce a signature. To increase the reliability and yield of embedded memories, many redundancy...