(RCS) frames which are systems that dwell of concrete columns and steel beams , by optimizing the act of compressive strength of concrete and bending strength of steel due to not only a decrease in building weight in comparison to concrete structures but also having a better action in long spans frames . In this paper for analysis RCS behavior, a category of nonlinear Push Over analyses were ...

Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit two’s complement or unsigned multiplication, or two independent 8-bit GF(28) multiplications in SIMD fashion. The combined multiplier is designed by modifying a c...

Motivating the perturbations of frames in Hilbert and Banach spaces, in this paper we introduce the invariance of Fr'echet frames under perturbation. Also we show that for any Fr'echet spaces, there is a Fr'echet frame and any element in these spaces  has a series expansion.

Scheming multipliers that are of high-speed, low power, and standard in design are of substantial research interest. By reducing the generated partial products speed of the multiplier can be increased. Several attempts have been made to decrease the number of partial products generated in a multiplication process. One of the attempt is Wallace tree multiplier. This paper aims at designing and i...

The finite field modular multiplier is the most critical component in the elliptic curve crypto processor (ECCP) consuming the maximum chip area and contributing the most to the device latency. Modular multiplication, point multiplication, point doubling are few of the critical activities to be carried out by multiplier in ECC algorithm, and should be managed without compromising on security an...

DESIGN AND IMPLEMENTATION OF LOW POWER MULTIPLIER USING VEDIC MULTIPLICATION TECHNIQUE Aniruddha Kanhe1, Shishir Kumar Das1 and Ankit Kumar Singh2 1Department of Electronics and Telecommunication Engineering NIT Raipur, India, E-mail: [email protected], [email protected] 2Department of Computer Science and Engineering NIT Raipur, India, E-mail: [email protected] In this paper a low...

The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooley multiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This system contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel conventional m...

In this paper, a single precision IEEE 754 floatingpoint multiplier with high speed and low power is presented. The bottleneck of any single precision floating-point multiplier design is the 24x24 bit integer multiplier. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 24x24 bit multiplication operation is...