A 2.4-GHz single-stage CMOS low noise amplifier (LNA) structure with ultra low power consumption is proposed. A current reuse technique is used to decrease power dissipation with increasing amplifier transconductance for the LNA. Thus, the same amplifier transconductance for the LNA will be achieved at decreased power dissipation. Also, due to the use of an inverter-type amplifier which has a s...

AbstractChopping is a proficient way to reduce the low frequency offset and 1/f noise in amplifiers. In this paper, a low power low noise CMOS chopper amplifier is presented. It is composed of a two stage amplifier. The first stage’s high output impedance and the equivalent Miller capacitance of the second stage constitute together a low pass filter, which reduces the power consumption. The cir...

This paper presents a two-stage low-noise ultra-wideband amplifier to obtain high and smooth gain in 180nm CMOS Technology. The proposed structure has two common source stages with inductive feedback. First stage is designed about 3GHz frequency and second stage is designed about 8GHz. In simulation, symmetric inductors of TSMC 0.18um CMOS technology in ADS software is used.Simulations results ...

a high accurate and low-voltage analog cmos current divider which operates with a single power supply voltage is designed in 0.18µm cmos standard technology. the proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. the proposed divider is modeled with neural network while tlbo algorithm is used to optimize it. the proposed optimization...

In this paper, a CMOS low power amplifier based on a high-quality active inductor and implemented by using 0.25-μm 1P5M CMOS standard technology is presented. The amplifier achieves power gain (S21) of 18dB within the -3dB cutoff frequency, bandwidth of 1.3GHz, and power consumption of 18mW under 2.5V power supply in 188 × 174μm silicon area. The input third-order intercept point (IIP3) and the...

This paper describes the design of a fully differential CMOS amplifier for clipping control circuit. The amplifier with specification of low settling time less than 5ns, high dynamic range above 90dB and low power supply of 3 volt is designed and realized in a 0.35 μm CMOS process with 3 volt power supply. Simulation confirm the presented design.

In this paper, a CMOS radio frequency (RF) multi-band band-pass amplifier using a high-Q active inductor load with a binary code band selector suitable for multi-standards wireless applications is proposed. By employing the improved high-Q active inductor including two bits binary controlled code, the RF multi-band amplifier operating at four different frequency bands is realized. The proposed ...

With the advancement of CMOS technology, the trend is to design transceivers using this technology with the aim of achieving full integration and reduced system cost. The power amplifier (PA) being one of the most important blocks of the wireless communication system is no exception. The aim of this work is to provide the study that allow the design of a singleended RF CMOS Class-E power amplif...

This paper presents the design and simulation of Low Noise Amplifier (LNA) in a 0.18μm CMOS technology. The LNA function is to amplify extremely low noise amplifier without adding noise and preserving required signal to noise ratio. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for...

The design of A 2.4-GHz CMOS Class E cascode power amplifier (PA) for GSM applications in TSMC 0.18-μm CMOS technology present in this paper. Proposed Class E cascode PA topology is a single-stage topology in order to minimize the device stress problem. A parallel capacitor is connected across the transistors for efficiency enrichment also for dominating the effect of parasitic capacitances at ...