Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture allows investigating the problems of implementi...

A polarimetry system for solar astronomy is presented. The system is based on a reconfigurable coprocessor attached to a conventional workstation. Although the computationally intensive parts of the application are performed in the host processor, the reconfigurable coprocessor plays a key role in taking charge of tasks that the host performs poorly, such as cycle-by-cycle data marshalling and ...

The Intel® Xeon PhiTM coprocessor platform enables offload of computation from a host processor to a coprocessor that is a fully-functional Intel® Architecture CPU. This paper presents the C/C++ and Fortran compiler offload runtime for that coprocessor. The paper addresses why offload to a coprocessor is useful, how it is specified, and what the conditions for the profitability of offload are. ...

In this paper we present a hardware realization of Kohonen's selforganizing feature map as a neural coprocessor connected to a personal computer (PC). We compare two concepts for this coprocessor, a vector-component-serial and processing-element-parallel array processor and a vector-component-parallel and processing-element-serial vector processor. Finally we give an overview about the whole sy...

In this paper, we present the implementation of a multi-mode crypto-coprocessor, which can support three different public-key cryptography (PKC) engines (NTRU, TTS, Pairing) used in post-quantum and identity-based cryptosystems. The PKC-based security protocols are more energy-efficient because they usually require less communication overhead than symmetric-key-based counterparts. In this work,...

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18μm CMOS. The coprocessor, which is used for embedded cryptogra...

This paper describes scalable Montgomery Multiplication (MM) coprocessor optimized for Altera NIOS embedded processor implemented in reconfigurable hardware. Features of the NIOS soft processor Avalon Bus are used to connect the coprocessor as a memory mapped peripheral so that the overall performance is improved. Implemented coprocessor performs modular MM with large numbers (up to 4096 bits),...