The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic ...

nowadays, it is common to find optimal point of the dynamic problem; dynamic problems whose optimal point changes over time require algorithms which dynamically adapt the search space instability. in the most of them, the exploitation of some information from the past allows to quickly adapt after an environmental change (some optimal points change). this is the idea underlining the use of memo...

This paper considers the problem of minimizing the mean tardiness of N jobs when the jobs are scheduled on a single machine. A simple algorithmic procedure is develop to obtain an optimal or a near optimal sequence for the N jobs while considering an equal penalty cost incurred to each job delivered later than its due date. The developed algorithm is applied to the several test problems. The re...

As the development of memory technology enables the production of high density memory, the use of dual port memory increases. Therefore, testing and diagnosis of the dual port memory is important. In this paper, when a defect is detected in the memory testing process, a new diagnosis algorithm that classifies specific types of defects is proposed. The new algorithm increases fault models effici...

how to cite this article: khosravi fard e, keelor jl, akbarzadeh bagheban ar, keith rw. comparison of the ravlt and digit test with typically achieving and gifted students. iran j child neurol. spring 2016; 10(2):26-37. abstract objective in this study, different kinds of memory were evaluated using rey auditory verbal learning (ravlt) test and were compared between two groups of typical and gi...

Memory built-in self-test (BIST) is a widely used technique to allow the and self-checking of embedded memories on chips after fabrication process. It can be by implementing standard testing algorithm available in EDA tool library or user-defined (UDA). This paper presents development software that automatically generates description file UDA deployed for memory BIST circuit implementation usin...

the phase transformation phenomenon due to the crystallographic change of shape memory alloys subjected to mechanical or thermal loading is very complicated. regarding the thermo-mechanical coupling effects in shape memory alloys, in case of high  loading rates, heat generation/absorption during the forward/reverse transformation, will lead in temperature-dependent variation and consequently af...

We have developed an algorithm by which to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This i; achieved by writing a routine called BIST Program by which only uses the existing ROM and creates no additional h...

Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this ...