Si and a-Ge, both the structure factor and V(k) consistently show two broad peaks at k1 = 3.2 nm -1 and k2 = 5.5 nm . The paracrystalline model (pc-Si) of a-Si consisting of nano-sized, strained crystalline grains embedded in a continuous random network (CRN) matrix is consistent with FEM data. The magnitude of V(k) varies with the paracrystallite size and volume fraction, but the first peak is...

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by ∼2/3 when the active region is scaled from Lactive=0.4 μm to 0.1 μm. Mobility can be lower by 50 % for narrow active widths resulting from the strain relaxation. The strain relaxati...

This thesis studied the application of strained-Si technology to RF power LDMOSFETs. Key issues for its implementation were determined to be thermal budget restrictions, gate oxide formation and impact ionization effects. 2D simulations were carried out to explore the design space of the strained-Si LDMOSFET. In order to address the thermal budget restrictions, use of a high-tilt implant for th...

Metal-oxide-semiconductor capacitors were fabricated on type-II staggered gap strained-Si/strained-Ge heterostructures epitaxially grown on relaxed SiGe substrates of various Ge fractions. Quasistatic quantummechanical capacitance-voltage (CV) simulations were fit to experimental CV measurements to extract the band alignment of the strained layers. The valence-band offset of the strained-Si/str...

Electro-thermal characteristics of strained-Si MOSFETs operating in high-current, high temperature regimes were investigated using device/circuit mixed mode simulations. The material parameters of strained-Si were calibrated for device simulations. Especially the phonon mean-free-path of strained-Si with high electric fields was estimated based on a full-band Monte Carlo device simulation. Desp...

Employment of the <100> channel direction in a strained-Si0.8Ge0.2 p-MOSFET provides a hole mobility enhancement as large as 25% and a parasitic resistance reduction of 20% compared to a <110> strained-Si0.8Ge0.2 channel p-MOSFET, which already has a better mobility and threshold voltage roll-off than the Si p-MOSFET. These results suggest that the <100> strained-SiGe-channel p-MOSFET can be us...

The band structure of strained Si ~4–10 ML! on ~001! GaAs, band lineups of the strained Si/~001!GaAs heterojunction, and confined energy levels of the Si3N4 /Si/GaAs quantum well have been calculated via a pseudopotential method. It has been found that in this technically important Si3N4 /Si/~001!GaAs structure, strained Si has a very narrow band gap ~0.34 eV! at the D' point in the Brillouin z...

The exponential miniaturization of Si CMOS technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In pre...

In this work, for the first time, the valence band offset, ∆EV, between strained Si and strained Si1-yGey on relaxed Si1-xGex, has been measured using a combination of experimentation and modeling. Such structures have been shown to offer large mobility enhancements for both electrons and holes, and knowledge of the band parameters is critical in order to optimize and predict device behavior [1...

Interfacial properties of in situ deposited Si3N4 /Si/p-GaAs metal-insulator-semiconductor structures have been investigated. Conductance loss measurements show that a minimum interface trap density as low as 5.5310 cm eV has been achieved on p-type GaAs by using a high quality strained Si interlayer. The quasistatic and high-frequency capacitance-voltage measurements as well as the theoretical...