in biaxially strained p-mosfet with si channel, formation of a parasitic parallel channel due to misalignment of energy bands degrades device performance by increasing off-state current. in this paper a new approach has been introduced to eliminate this parasitic channel by increasing the dopant concentration of virtual substrate up to . using simulation the impact of this method on the parasit...

SiGe quantum devices were demonstrated by AFM oxidation and selective wet etching with features size down to 50 nm. To passivate the devices and eliminate the interface states between Si/SiO2, low temperature regrowth of epitaxial silicon over strained SiGe has been tested. The silicon regrowth on Si0.8Ge0.2 was done by rapid thermal chemical vapor deposition (RTCVD) at 700 oC using a hydrogen ...

A novel structure of double-gate (DG) NMOSFET, which is formed by a strained silicon (Si) channel by using Si/Si1−xGex/Si, is proposed for the improvement of device characteristics. For analyzing the nano-scale DG MOSFET, a two-dimensional quantum-mechanical (QM) approach for solving the coupled Poisson-Schrödinger equations is reported. The advantages of a strained Si channel of DG MOSFET are ...

The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Ru...

The development of high performance nano-electron-emitter arrays with well reliability still proves challenging. Here, we report a featured integrated nano-electron-emitter. The vertically aligned nano-emitter consists of two segments. The top segment is an intrinsically lightly n-type doped ZnO nano-tip, while the bottom segment is a heavily p-type doped Si nano-pillar (denoted as p-Si/ZnO nan...

Deep submicron strained-Si n-MOSFET’s were fabricated on strained Si/relaxed Si0 8Ge0 2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices ...

Strained Siand SiGe-based heterostructure MOSFETs grown on relaxed SiGe virtual substrates exhibit dramatic electron and hole mobility enhancements over bulk Si, making them promising candidates for next generation CMOS devices. The most heavily investigated heterostructures consist of a single strained Si layer grown upon a relaxed SiGe substrate. While this configuration offers significant pe...

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility ...

As complementary metal-oxide-semiconductor field-effect transistors (MOSFETs) scale, strained Si and SiGe technology have received more attention as a means of enhancing performance via improved carrier mobility. One of the biggest challenges for strained Si and SiGe technology is Si-Ge interdiffusion during thermal processing. Two different aspects of Si-Ge interdiffusion are explored in this ...