نتایج جستجو برای: trade architecture

تعداد نتایج: 327127  

2000
Jakob Axelsson

This paper presents a model for estimating the total cost of a proposed electronic architecture for embedded, distributed, real-time systems. The main purpose of the model is to allow system engineers to compare different solution alternatives with respect to cost, in order to perform an early optimization. This is necessary to cope with the complexity of such systems, and make them profitable ...

2007
Frank Bouwens Mladen Berekovic Andreas Kanstein Georgi Gaydadjiev

Reconfigurable computational architectures are envisioned to deliver power efficient, high performance, flexible platforms for embedded systems design. The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer a tool flow to design sparsely interconnected 2D array processors with an arbitrary number of functional u...

Journal: :Computer-Aided Design 2004
Laurent Denis Yvon Gardan Estelle Perrin

The DIJA project is a web-based CAD system accessible to any user (from neophyte to expert) and from a simple desktop computer. Its modeling approach is based on a top-down methodology and takes into account trade information. In this paper, we propose a network architecture based on a replication process and a multi-level language to manage the consistency between the client model and the serv...

2011
C. Zambelli M. Indaco M. Fabiano S. Di Carlo P. Prinetto P. Olivo D. Bertozzi

In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller archi...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه تهران 1381

در دو دهه گذشته پردازنده ها ‏‎(dsp processor)‎‏ ، بازار تراشه های همه منظوره محاسبات ‏‎dsp‎‏ را در اختیار داشته اند . پیشرفت در ساخت مدارهای دیجیتال ، افزایش تعداد گیتهای منطقی قابل پیاده سازی در یک تراشه را در پی داشته است . به نظر می رسد پردازنده ها ‏‎(programmable architecture)‎‏ امکان حداکثر بهره برداری از این ظرفیتهای جدید را نداشته و نیاز به بازنگری دارند. معماری بازپیکرپذیر ‏‎(reconfigur...

Journal: :Computers & Electrical Engineering 2009
Miguel Morales-Sandoval Claudia Feregrino Uribe René Cumplido Ignacio Algredo-Badillo

A hardware architecture for GF(2 m ) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parametrizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.

2006
Michael Mattsson Håkan Grahn Frans Mårtensson

The software architecture has been identified as an important part of a software system. Further, the software architecture impacts the quality attributes of a system, e.g., performance and maintainability. Therefore, methods for evaluating the quality attributes of software architectures are important. In this paper, we present a survey of software architecture evaluation methods. We focus on ...

Journal: :Environmental Health Perspectives 2001
L Claudio

Focus " The World Trade Center is a living symbol of man's dedication to world peace.. .. [T]he World Trade Center should. .. become a representation of man's belief in humanity, his need for individual dignity, his beliefs in the cooperation of men, and through cooperation, his ability to find greatness. " Minoru Yamasaki, chief architect of the World Trade Center quoted in Architects on Archi...

2017
Sonda CHTOUROU Zied MARRAKCHI Emna AMOURI Vinod PANGRACIOUS Mohamed ABID Habib MEHREZ

Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design’s big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental met...

2012
Patrik Goorts Sammy Rogmans Philippe Bekaert

In this paper, we investigate demosaicing of raw camera images on parallel architectures using CUDA. To generate high-quality results, we use the method of Malvar et al., which incorporates the gradient for edgesensing demosaicing. The method can be implemented as a collection of finite impulse response filters, which can easily be mapped to a parallel architecture. We investigated different tr...

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