A hybrid network is proposed in dynamic CMOS XOR/XNOR gate to avoid signal skew and reduce the power consumption. Compared to the standard N type dynamic gate leakage power, dynamic power and layout area of the novel XOR/XNOR gate are reduced. In this paper we studied different technologies, their merits and demerits. Comparison of different technologies is completely on the basis of leakage po...

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272μW in 0.35μm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of ...

This paper proposes a model that predicts the complexity of Boolean functions with only XOR/XNOR min-terms using back propagation neural networks (BPNNs) applied to Binary Decision Diagrams (BDDs). The BPNN model (BPNNM) is developed through the training process of experimental data already obtained for XOR/XNOR-based Boolean functions. The outcome of this model is a unique matrix for the compl...

In this paper, logical masking capability of commonly used logic gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR, when subject to single/multiple input faults, are analyzed from a mathematical perspective. A new metric, called Gate Error Metric (GEM) is proposed to study the extent of output error in these gates when subject to potential input fault occurrences, where less value of GEM implie...

In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 0.964] GHz with [279.429 16.515] μW power consumption variation. VCO designed with five XNO...

The multipliers are the key structure for designing high performance digital systems. Design considerations of multiplier include high speed, less power consumption, less PDP (power-delay product) and regularity of layout. These design parameters make it suitable for various compact low power VLSI implementations. This paper presents an application of the proposed XNOR-XOR cell for a 2x2 array ...

This article presents two new, reconfigurable multi-input floating-gate circuits able to produce either the INVERTED SUM / INVERTED CARRY functions for a FULL-ADDER, XNOR / NAND, or XOR / NOR. The circuits contain four MOSFETs and fourteen or nine capacitors, respectively. SPICE simulations are shown, demonstrating the principal operation, together with preliminary measurements indicating that ...

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, wit...