This paper presents a new design for 14 transistor single bit full adder, implemented using five transistor XNOR/XOR cell and transmission gate multiplexer. For transmission gate multiplexer complementary gate control signals are required and in 14 transistor full Adder both XOR and XNOR signals are generated. XNOR/XOR cell shows high power consumption than single XNOR gate. So, 8 transistor fu...

Exclusive-NOR (XNOR) gates are important in digital circuits. This paper proposes the novel design of 2T XNOR gate using pass transistor logic. The proposed circuit utilizes the least number of transistors and no complementary input signal is used. The design has been compared with earlier designed XNOR gates and a significant improvement in silicon area and power-delay product has been obtaine...

We propose two efficient approximations to standard convolutional neural networks: Binary-Weight-Networks and XNOR-Networks. In Binary-WeightNetworks, the filters are approximated with binary values resulting in 32× memory saving. In XNOR-Networks, both the filters and the input to convolutional layers are binary. XNOR-Networks approximate convolutions using primarily binary operations. This re...

Exclusive NOR (XNOR) gates are very important in electronics department. This is widely used in digital circuits. This paper proposes the novel design of 2T XNOR gate using pass transistor logic. The proposed circuit has the minimum transistor count and there is no complementary input signal is used. This design has been compared and analyzed with earlier designed XNOR gates and a significant i...

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the c...

ABSTRACT : In this paper, we review various design techniques for XOR-XNOR circuits as these circuits are basic building blocks of many arithmetic circuits. The XOR and XNOR circuits can be implemented in different architectures by using different circuit designs. This paper evaluates and compares the performance of various design techniques of XOR-XNOR circuits. The performance of the XOR-XNOR...

As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...

A Multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, Digital Signal Processors (DSPs), Microprocessors etc., A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses 4:2, 5:2 compressors and a Carry Select Adder (CSA) to reduce the latency and power consumption. In conventional methods, 10T XNOR s...

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps n any high speed ALUs that can be used varies processors and applicable for IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are fundamental building block perform arithmetic operation. In this paper, different types high-speed, 6T-XOR/XNOR-cell de...

Article history: Available online 17 February 2011 Keyword: Dynamic XOR/XNOR Gate Leakage Power Variation 0167-9317/$ see front matter 2011 Elsevier B.V. A doi:10.1016/j.mee.2011.02.068 ⇑ Corresponding author. Tel.: +86 15001166864. E-mail address: [email protected] (J. A hybrid network technique is proposed in dynamic CMOS XOR/XNOR gate to reduce the power consumption, save the layout...