Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing gap between the memory and processor speeds. With the advent of multithreaded processors, it becomes feasible to concurrently fetch data and compute in two cooperating threads. A technique is presented to generate these...

This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compressed form. However, decompression time causes a critical effect on the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed cache architecture. This paper sugges...

A very fast recovery voltage regulator for large capacitive loads is presented. A feedback cascode technique is used to achieve high recovery speed when a previously discharged capacitance is connected to the regulator output. The design has been optimized for a word-line read voltage regulator for a 4-level (2-bit/cell) 32-Mcell Flash memory (64 Mbits). Computer simulations showed that recover...