Performance analysis plays an essential role in achieving a scalable performance of applications on massively parallel supercomputers equipped with thousands processors. This paper is empirical investigation to study, depth, the two most common High-Performance Computing architectures world. IBM has developed three generations Blue Gene supercomputers—Blue Gene/L, P, and Q—that use, at large sc...

This document describes the use of the FPGA coprocessor microEnable as Read Out Buffer (ROB) hardware for the trigger system of the Atlas detector. It shows with performance measurements the possibilities of FPGA hardware to buffer and manipulate data received from the detector very fast. It points out that FPGA hardware can be used successfully in the Atlas trigger environment.

This paper describes an experimental system designed for development of real time voice synthesis applications. The system is composed from a DSP coprocessor card , equipped with an TMS320C25 or TMS320C50 chip, voice acquisition module (ADDA2) ,host computer (IBM-PC compatible), software specific tools.

In this paper we explore pseudo-random number generation on the IBM 4758 Secure Crypto Coprocessor. In particular we compare several variants of Gennaro's provably secure generator, proposed at Crypto 2000, with more standard techniques based on the SHA-1 compression function. Our results show how the presence of hardware support for modular multiplication and exponentiation aaects these algori...

Implementation setup The Keccak hardware reference designs consists of two rather different implementations. the high_speed_core design is, as the name suggest, a self contained high performance design. The low_area_copro on the other hand, is a small design where the state memory is external from the rest of the design. This allows the Keccak coprocessor to share memory with other design entit...

this paper describes a block that can be added to a crypto-processor embedded on a FPGA. This block enables to simulate the coprocessor behaviour when faults are injected. Three fault models are used and an example with AES is given. The aim of such a block is to speed up the test of countermeasures on a FPGA before running the chip in fab.

This work proposes a complete and side-channel proof solution for an FPGA implementation of AES. An unsecured implementation is extended to a secured version by using a masking algorithm. Our solution is implemented as an FPGA prototype, but in the future it can be easily used in a crypto-coprocessor on a smartcard.

This paper describes design aspects of a system specialized in the acquisition and processing of brain potentials (EEGsignals).The system is composed from a PC-host computer equipped with an DSP based coprocessor for accelerating certain computing-intensive operations (FFT) and an acquisition unit (Head-box) serially coupled with the stand unit.

A tool called MEAT is presented which automatically synthesizes transistor level, CMOS, asynchronous control circuits from nite state machine based speci cations. MEAT has been used to synthesize the control circuits for an asynchronous 300,000 transistor communication coprocessor. Keyword Codes: B.6.1; B.6.3; B.7.2

This document describes ASIC and FPGA implementations of the hash function Hamsi. The results show that Hamsi can be efficiently implemented in hardware with small area. We also point out several optimization methods targeting different design goals. 1 Design Guideline The current implementations are straightforward realizations of the Hamsi hash function family. In other words, higher throughp...