This paper presents the design, implementation and measurements of a BiCMOS integrated tunable Low Noise Amplifier for 5 GHz WLAN applications. It consists of a cascode gain cell, noise and power matched to a 50 Ω input source, and power matched to a 50 Ω load. In order to broaden the available bandwidth, the output matching network is modified by means of a shunt varactor, thus allowing the tu...

This paper describes a 2.4-GHz fully-integrated front-end receiver including single-pole triple-throw (SP3T) switch and low-noise amplifier (LNA) with bypass function, which was fabricated in 0.25 μm GaAs pHEMT process. An asymmetrical SP3T architecture is incorporated to enable the operate four modes. The exploration of impedance voltage gain behavior proposed LNA help establish matching netwo...

This dissertation describes the design of a CMOS 900-MHz bandpass amplifier that is suitable for RF transceivers. The work employs the state-of-art inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input matching networks on-chip. A Q-compensation circuit is included to achieve a 25-MHz 3-dB bandwid...

A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field and other non-idealities have some impacts on the TTD cell's devices. One of vulnerable specifications cells their variation. While works a line, must constant robust frequency band. For this matter, body bias technique presented applied to inductor-less ...

In this paper, a lattice network-based second-order all-pass filter (APF) design is presented. Unlike previously published works, floating active inductors (FAIs) are used in the topology. Inductance (L) and quality factor (Q) tunability of Q-enhanced FAIs employed to ensure designed APF robust process-voltage-temperature (PVT) variations make filter’s group delay responses constant for wide fr...

In this paper, we propose a doping-less dual-material double-gate tunnel field-effect transistor with P+ pocket (PP-DMG TFET). This gate-engineered technique is typically used in MOSFET to improve device performance. The embedded at the source side enhance performance of pocket-engineered PP-DMG TFET device. paper compares four DG-TFET-based devices, i.e. single-material gate (SMG), (PP-SMG), (...

This paper presents a noise reduction technique using common-mode feedback in active CMOS mixers. The proposed decreases the noise, thus reducing common-to-differential conversion arising from mismatch and process variations. In addition, reduces sensitivity to process, voltage, temperature (PVT) variations due negative feedback. A theory is adopted analyze low-noise performance of technique. t...

VASANI, ANAND JITENDRA Design of Frequency Agile Circuits Using Barium Strontium Titanate Varactor. (Under the direction of Prof. Kevin G. Gard). Multi-standard and multi-band radio are the next milestone in the ever developing radio industry. Frequency agile circuits are an enabling technology which allows us to achieve this goal. It is a low cost and efficient technology that provides the nec...

This article introduces a new discrete-time (DT) charge-sharing (CS) low-pass filter (LPF) that achieves high-order filtering and improves its stopband rejection while maintaining reasonable duty cycle of the main clock at 20%. It proposes two key innovations: 1) linear interpolation sampling capacitor 2) charge re-circulation history capacitors for deep rejection. Fabricated in 28-nm CMOS, pro...