Three high voltage modulators used during testing and operation of the Tevatron Electron Lens (TEL) at Fermilab will be described. Short high voltage (0 to ~20kV) pulses from these modulators vary the anode-cathode voltage of the TEL electron gun to control the magnitude of the electron beam current. The trio of modulators include a low repetition rate MOSFET-based pulser, a fast ionization dev...

Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. A lightly doped channel has been taken to enhance the device performance and reduce short channel effects (SCEs) such as drain induced barrier lowering (DIBL), sub threshold slope (SS), hot carrier effects (HCEs), channel...

Simulators in power electronics are less developed than in other electronic fields. The main modelling methods are between the numerical simulation of semiconductor device equations that hardly simulate circuits, and equivalent circuit models that show poor accuracy. We propose the application of the bond graph techniques to model modular power semiconductor devices. Furthermore, the IGBT is a ...

The conventional MOSFETs are likely to reach scaling limitations at gate lengths between 15 and 10nm. The double-gate MOSFET architecture is a promising candidate for scaling to 10nm and below in line with the requirements of the International Technology Roadmap. However, it is expected that direct source-drain tunnelling would be a major limiting factor in the double-gate device. In this paper...

OVERVIEW: Silicon semiconductor (MOSFET: metal-oxide semiconductor field-effect transistor) dimensions are approaching the nanometer scale. The gate electrode size has already been reduced to 50 nm or less for the most advanced 90-nm technology nodes, and for the 65-nm nodes the size is expected to be 25 nm. A new guideline to replace the scaling rule is needed, and making use of the strain eff...

Device and circuit performance such as drain current and delay time varies stochastically due to uncontrollable factors in the fabrication processes. In this paper, a new method that represents the variation of the performance as worst case parameters in a MOSFET model is proposed. The variation of the performance can be expressed as a linear combination of several process-related parameters of...

InGaAs is a promising candidate as an n-type channel material for future CMOS due to its superior electron transport properties. Great progress has taken place recently in demonstrating InGaAs MOSFETs for this goal. Among possible InGaAs MOSFET architectures, the recessedgate design is an attractive option due to its scalability and simplicity. In this thesis, a novel selfaligned recessed-gate ...

A lateral trench-gate power metal-oxidesemiconductor on 4H-SiC is proposed. The device consists of two separate trenches in which two gates are placed on both sides of Pbody region resulting two parallel channels. Enhanced current conduction and reduced-surface-field effect in the structure provide substantial improvement in the device performance. Using two dimensional simulations, the perform...