A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout o...

Educators continue to face pressure from students and industry to employ the newest technology in the classroom. With regard to VLSI design and the role of CAD tools, a balance must be struck between fundamentals and training to a particular software package. This paper describes a semester project, suitable for an undergraduate VLSI course, which emphasized the design process, rather than indi...

High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult to combine these objectives into a single cost function, as this effectively requires prioritisation of the parameters, which may reduce the overall quality of the solution. A superior approach is to simultaneously op...

We investigate potential uses of aspect-oriented programming in the context of object-oriented C++ frameworks used in the development of VLSI CAD applications. We use existing applications to explore the use of different kinds of aspects. We differentiate between framework-based aspects and application-specific aspects. Framework-based aspects modularize cross-cutting code based on how an appli...

In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems. This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three. A transparent relationship between the fitting parameters and the p...

Sparse linear systems are found in a variety of scientific and engineering problems. In VLSI CAD tools, DC circuit analysis creates large, sparse systems represented by matrices and vectors. The algorithms designed to solve these systems are known to be quite time consuming and many previous attempts have been made to parallelize them. Graphics cards have evolved from specialized devices into m...

The SPEC benchmark system has traditionally been used for evaluating computer architec-tures. However, this system is too general and does not accurately reeect the performance of architectures on domain-speciic applications. Moreover, the CPU95 benchmark suite used in the SPEC system is compute-intensive, while many important domains of applications have memory intensive algorithms. In this wo...

A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simpliied linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used...