This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce switched capacitance of the clock tree. The clock tree topology is constructed based on the locations ...

Process-variation induced skew has become one of the major contributors to the clock-skew in advanced technologies. Since process-variation induced skew is roughly proportional to clock-delay, it is preferable to design zero-skew clock-trees and have minimum clock-delay to reduce both unintentional and process-variation induced skews. In this paper, we propose a zero-skew buffered clock-tree sy...

The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equ...

Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our s...

It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) ...

An important problem in VLSI design is distributing a clock signal to synchronous elements in a VLSI circuit so that the signal arrives at all elements simultaneously. The signal is distributed by means of a clock routing tree rooted at a global clock source. The difference in length between the longest and shortest root-leaf path is called the skew of the tree. The problem is to construct a cl...