The effect of the swirl clocking on three-dimensional nozzle guide vane (NGV) is investigated using computational fluid dynamics. research reports loss characteristics leaned and swept NGVs influence clocking. are built by stacking same 2D profile along different linear axes, characterized angles with respect to normal or radial direction: ε = −12° ~ +12° for γ −5° +10° airfoils. A total 40 mod...

Level-clocked designs that employ a two-phase, nonoverlapping clocking scheme have the theoretical potential to operate up to twice as fast as edge-triggered designs. We have run experiments that demonstrate, however, that edge-triggering is often just as fast as two-phase clocking, and that the speed potential of two-phase clocking is generally not obtained except when the delay between any tw...

This work shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct numbe...

Communication between independently-clocked digital subsystems typically involves a nite probability of synchronization failure whose minimization introduces delays and consequent performance costs. This paper explores a technique that eliminates both the inherent unreliability of such communication and the performance overhead it implies. Our approach maintains a known phase relationship betwe...

This paper enumerates a low power, high speed design of flip-flop having less number of transistors. In flip-flop design only one transistor is being clocked by short pulse train which is known as True Single Phase Clocking (TSPC) flip-flop. The true single-phase clock (TSPC) is common dynamic flip-flop which performs the flip-flop operation with little power and at high speeds. In this paper, ...

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...