In this paper is presented a novel constant transconductance CMOS differential amplifier. The circuit uses a modified CMOS inverter to process polarisation currents of the complementary differential amplifier in order to maintain constant transconductance over the entire common-mode input voltage range. Simulation shows error less than ±6.12 % for a single supply voltage of 1.5 V. Key-Words: lo...

In this work, we analyze the effects of an inter-stage capacitor located between the power stage input and the driver stage output on the overall efficiency of a RF CMOS power amplifier and on gate-drain reliability problems. To verify the analyzed effects, we designed a RF CMOS power amplifier with a center frequency of 1.85GHz. Class-D amplifiers with a feedback resistor are used as driver st...

This paper presents a two-stage low-noise ultra-wideband amplifier to obtain high and smooth gain in 180nm CMOS Technology. The proposed structure has two common source stages with inductive feedback. First stage is designed about 3GHz frequency and second stage is designed about 8GHz. In simulation, symmetric inductors of TSMC 0.18um CMOS technology in ADS software is used.Simulations results ...

The comparator is designed in pipelined ADC. FINFET is the technology which performs the dual gate MOSFET. This thesis focuses on the high-speed design of pipelined ADC. In the meanwhile, we try to minimize the power dissipation as well. In this thesis, A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC )in HSPICE .And also we compare the pow...

In this paper, a CMOS Multi-band LNA using High-Q active inductors load with a binary code band selector suitable for multi-standards wireless applications is proposed. Using an improved high-Q active inductor including two bits binary controlled code, the multi-band low noise amplifier operating at four different frequency bands is realized. The proposed amplifier is designed in TSMC 0.18-um C...

Since the fabrication of active electrodes has been reported and their beneficial effects scientifically confirmed, we present a CMOS bioelectric amplifier with DC rejection designed for active electrode in this paper. Analysis, design and post simulation results will be described in detail. The amplifier operating at ±0.9V supply voltage has a mid-band gain of 40dB with ±300mV dc offset reject...

This paper presents a 30dBm (1W) class-E power amplifier projected in a standard 0.18-μm CMOS technology. The power amplifier (PA) consists in two differentials stages. The main stage employs a cascode class-E RF power amplifier with a self-biasing circuit. The driver stage uses the technique of Injection-Locking to substantially reduce the input power signal, maintaining a high gain. At 2.45 G...

A novel low noise trans-impedance amplifier is proposed using low cost 0.18 µm CMOS technology. A resistive-capacitive feedback is used to extend the bandwidth of the amplifier. As the structure is inductor less, it is suitable for low cost integrated optical interconnects. In this paper Improved Particle Swarm Optimization have applied to determine optimal trans-resistance and noise of propose...

This paper presents the design and simulation of Low Noise Amplifier (LNA) in a 0.18μm CMOS technology. The LNA function is to amplify extremely low noise amplifier without adding noise and preserving required signal to noise ratio. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for...

In this paper two dimensional wave propagation is used for power combining in drain nodes of a distributed amplifier (DA). The proposed two dimensional DA uses an electrical funnel to add the currents of drain nodes. The proposed structure is modified due to gate lines considerations. Total gain improvement is achieved by engineering the characteristic impedance of gate lines and also make appr...