This paper presents a variable frequency multiplier technique (VFX) that enables design of converters for wide input and/or output voltage ranges while preserving high efficiency. The technique is applied to an LLC converter to demonstrate the effectiveness of this technique for converters having wide input voltage variation such as universal input power supplies. This technique compresses the ...

A computer program has been written to investigate the design tradeoffs of high frequency diode frequency multipliers. Velocity saturation and breakdown have been included in a device model that is part of a nonlinear multiple reflection simulation. The device doping, epitaxial layer length and velocity vs. electric field curve are input parameters. The program has a search routine to match the...

This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the ...

Cell voltage equalizers are necessary to ensure years of operation and maximize the chargeable/dischargeable energy of seriesconnected supercapacitors (SCs). A two-switch voltage equalizer using a series-resonant voltage multiplier operating in frequency-multiplied discontinuous conduction mode (DCM) is proposed for series-connected SCs in this paper. The frequency-multiplied mode virtually inc...

The aim of delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. By applying the logic to the pulse generator and multiplication-ratio control logic design, the frequency of the delay is determine...

The multipliers are the key structure for designing high performance digital systems. Design considerations of multiplier include high speed, less power consumption, less PDP (power-delay product) and regularity of layout. These design parameters make it suitable for various compact low power VLSI implementations. This paper presents an application of the proposed XNOR-XOR cell for a 2x2 array ...

In this study, a C~K band frequency synthesizer used in broadband electronic warfare equipment was designed, developed, and the measurement results were presented. The structure of designed generates signal up to 6 GHz using only direct digital synthesizer(DDS) without mixer or multiplier. For signals above frequency, uses addition, variable sampling DDS circuit improve quality by reducing spur...

In this paper, a grounding capacitance multiplier is presented. This block is very important because he presents a better solution to resolve the problems occured by the integration of high capacitance value or the problem of tuning that value of the capacitance. We emphasize the fact that the presented applications are well suited for integration since their value can be tuned by simple action...