Article history: Received 29 June 2010 Received in revised form 18 October 2012 Accepted 18 October 2012 Available online 20 November 2012 0045-7906/$ see front matter 2012 Elsevier Ltd http://dx.doi.org/10.1016/j.compeleceng.2012.10.00 q Reviews processed and approved for publication ⇑ Corresponding author. Tel.: +3

Logic built-in self-test (LBIST), is a mechanism that lets an (IC) test the integrity of its own digital logic structures. LBIST operates by stimulating the logic-based operations of the IC and then detecting if the logic behaved as intended. The main advantage of LBIST is that it provides test capability without an external tester. In particular, safety-critical designs need to be tested and r...

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K to 800K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Compar...

True software-defined radio cellular base stations require extremely fast data converters, which can currently not be implemented in semiconductor technology. Superconductor Niobium-based delta ADCs have shown to be able to perform this task. The problem of testing these devices is a severe task, as still very little is known about possible defects in this technology. This paper shows an approa...

Marco d’Ischia 1,* ID and Daniel Ruiz-Molina 2,* ID 1 Department of Chemical Sciences, University of Naples Federico II, Via Cintia 4, I-80126 Naples, Italy 2 Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and BIST, Campus UAB, Bellaterra, 08193 Barcelona, Spain * Correspondence: [email protected] (M.d.I); [email protected] (D.R.-M.); Tel.: +39-081-674132 (M.d.I.); +34-093-737...

1.1 1:30 p.m. "An Efficient Self-Test Structure for Sequential Machines" S.Z. Hassan Rolm Mil-Spec Computers In this paper, a BIST structure for sequential machines is presented. The approach requires augmentation of the machine by the addition of an extra input and some logic. The test sequence is independent of the function implemented and depends only on the number of input combinations and ...

We present a new pseudorandom testing algorithm f o r the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed f o r the detection of coulping faults. A s a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible.