This chapter outlines and discusses important microand nanofabrication techniques. We start with the most basic methods borrowed from the integrated circuit (IC) industry, such as thinfilm deposition, lithography and etching, and then move on to look at microelectromechanical systems (MEMS) and nanofabrication technologies. We cover a broad range of dimensions, from the micron to the nanometer ...

This paper is based on analysis of a common source - common gate low noise transconductance amplifier (CS-CG LNTA). Conventional noise analyses equations are modified by considering to the low output impedance of the sub-micron transistors and also, parasitic gate-source capacitance. The calculated equations are more accurate than calculated equations in other works. Also, analyses show that th...

We present a simple and efficient method for the extraction of thermal channel noise of MOS FET’s in quarter and sub-quarter micron technologies from NF50 (noise figure at 50 Ohm source resistance) measurements. For shorter channel lengths the experimental results shows a continuously rising deviation from the classical long channel theory [1]. For a 0.18 μm technology a γ≈6 instead of 2/3 in s...

Optical scattering has traditionally limited the ability to focus light inside scattering media such as biological tissue. Recently developed wavefront shaping techniques promise to overcome this limit by tailoring an optical wavefront to constructively interfere at a target location deep inside scattering media. To find such a wavefront solution, a "guide-star" mechanism is required to identif...

The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Applica...

Rising levels and spread in IDDQ values render single threshold IDDQ testing obsolete for highperformance chips for deep sub-micron technologies. Increased inter-die and intra-die variations cause unacceptable yield loss with a single pass/fail limit. Use of spatial information to estimate fault-free IDDQ is investigated. Flush delay information is used to refine this estimate under varying pro...

For next generation mixed signal ICs, the integration of Design-for-Testability and Built-In Self-Test structures is expected to be of crucial importance for satisfying quality and economic demands. The judgment and evaluation of such testability optimisations, however, requires a better understanding of circuit specific failure modes in deep sub-micron technologies. This paper presents fault s...

Recent technology improvements are leading to significant advances in telecommunications. New sub-micron technologies allow us to design high speed digital processors and high-speed, high-resolution data converters. These basic components push the analog-digital border close to the antenna and favor the implementation of complex digital algorithms. Various system architectures are examined and ...

The use of embedded DRAM technology has become widespread, especially in higher-end system designs, because of its superior performance, silicon area savings, and low power compared to discrete memory solutions. Traditionally, in cost-sensitive consumer applications, large memory arrays of 64 megabits and above were usually better suited to discrete commodity memory implementations. But as the ...