— It is well known that frequency response masking (FRM) FIR digital filters can be designed to exhibit very sharp-transition bands at the cost of slightly larger filter lengths as compared to the conventional FIR digital filters. The FRM FIR digital filters permit efficient hardware implementations due to an inherently large number of zero-valued multiplier coefficients in their transfer funct...

This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier, energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multipli...

We describe a method for removing noise from digital images, based on a statistical model of the coefficients of an overcomplete multiscale oriented basis. Neighborhoods of coefficients at adjacent positions and scales are modeled as the product of two independent random variables: a Gaussian vector and a hidden positive scalar multiplier. The latter modulates the local variance of the coeffici...

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of sh...

Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than...

The hardware complexity of digital filters is mainly dominated by the coefficient multipliers. Implementing fixed-point coefficient multiplication as a network of adders, subtractors, and shifters, yields lower power consumption. In such filters the number of adders (and subtractors) determines the implementation cost. The reason is that shifts are implemented as hard-wired inter-block connecti...

A new bi-directional bit serial-parallel multiplication architecture is presented. The proposed structure is regular and modular, and requires nearest neighbour communication links only, which makes it more efficient for VLSI implementation. Furthermore, a judicious deployment of larches in the circuit ensures that the multiplier operates on two coefficients of the multiplicand at the same time...

The multiplier uses LUT’s as memory for their computations. The antisymmetric product coding (APC) and odd-multiple-storage (OMS) techniques were proposed for look-up-table (LUT) design. The APC and OMS techniques used for efficient memory-based multiplication. Therefore the combined approach provides a reduction in LUT size to onefourth of the conventional LUT. APC approach is combined with th...

Nowadays, the clustering of proteins and enzymes in particular, are one of the most popular topics in bioinformatics. Increasing number of chitinase genes from different organisms and their sequences have beenidentified. So far, various mathematical algorithms for the clustering of chitinase genes have been used butmost of them seem to be confusing and sometimes insufficient. In the...