This paper presents a subcircuit compact model to study the dc characteristics of a partially depleted (PD) SOI laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) utilizing the HiSIM-HV compact model. Our model accounts both for the high-voltage and the floating-body effects such as the quasi saturation effect, the impact ionization in the drift region and the famou...

This paper presents a novel statistical characterization for accurate timing and a new probabilistic based analysis for estimating the leakage power in Partially-Depleted Silicon-OnInsulator (PD-SOI) circuits in BSIMSOI3.2 100nm technology. This paper shows that the accuracy of modeling the leakage current in PD-SOI CMOS circuits is improved by considering the interactions between the subthresh...

Substrate engineering [1] has enabled the industry to overcome many of the limitations encountered by traditional scaling. As a result, device architecture and engineered substrates have become strongly coupled, a coupling that is growing stronger as the IC industry moves to the 32 nm technology node and beyond. Substrate engineering started in earnest with the industry transition to SOI wafers...

Abstract In this work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests...

Dynamic Threshold (DTMOS) circuits have been proposed as a circuit style for low-power VLSI systems that takes advantage of the independent body control in partially-depleted SOI. As SOI technologies have scaled, the increasing body capacitance and body resistance have limited the effectiveness of DTMOS circuits that drive the body at the same speed as the gate. An analysis of DTMOS in 0.13μm P...

Introduction With technology scaling rapidly, there is increased need for improved performance. While improved performance can be achieved with lower threshold voltages, leakage will be a major issue at technologies below 0.1μm. Interconnect scaling is not expected to keep up with component scaling, resulting in higher capacitance losses and challenges in signal routing. We consider how scaling...

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW.

The proliferation of both Partially Depleted SiliconOn-Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SO1 complicate testing. This paper describes the issues of testing domino circuits fabricated in SO1 technology and...