The input power requirements for accessing H-mode at low density and maintaining it during the density ramp in ITER is addressed by statistical means applied to the international H-mode threshold power database. Following the recent addition of new data, the improvement of existing data and the improvement of selection criteria, a revised scaling law that describes the threshold power required ...

This paper presents a new low-power Threshold Logic family featuring self lock-out and run-time reprogrammability. The simulated results have shown that, the proposed Threshold Logic dissipates between and less power and between and less energy, at , when compared with previous similar Threshold Logic families. Moreover, at , it has between and less energy and between and ! less dissipated powe...

Abstract: In this study, the effects of variation of thickness and the number of quantumwells as well as the contact length were investigated. In this paper, a vertical cavity surfaceemitting laser was simulated using of software based on finite element method. Thenumber of quantum wells was changed from 3 to 9 and the results which are related tooutput power, resonance ...

The use of dual threshold voltages can signiicantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consum...

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold—high Vth for good standby power and low Vth for h...