Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...

We describe the design of an embedded 128-Kb Silicon-OnInsulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25m fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presen...

A voltage-controlled negative-differential-resistance device using a merged integrated circuit of two n-channel enhancement-mode MOSFETs and a vertical NPN bipolar transistor, called vertical Lambda-bipolar-transistor (VLBT), is presented for memory application. The new VLBT structure has been developed and its characteristics are derived by a simple circuit model and device physics. A novel si...

Double Data Rate Dynamic Random Access Memory (DDR DRAM) has become important to develop a low-power high performance DCC(Duty Cycle Corrector) with better duty cycle accuracy. DDR DRAM increases the speed using Successive Approximation Register Duty Cycle Corrector (SAR DCC). The proposed DCC circuit will be implemented in a 0.18um CMOS process. Here, Adjuster circuit delay line is being modif...

Abstract: Analog sampling systems based on switched capacitor techniques offer performance superior to that of flash A/D converters with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes a 500 MHz switched capacitor analog waveform sampling circuit for the camera electronics of the Cherenkov telescope. An experimental 4 channel analog memory wit...

Bias Temperature Instability (BTI) is a major reliability issue in Nano-scale CMOS circuits. BTI effect results in the threshold voltage increase of MOS devices over time. Given the Process, Voltage, and Temperature (PVT) dependence of BTI effect, and the significant amount of PVT variations in Nano-scale CMOS, we propose a method of combining the effects of PVT variations and the BTI effect fo...

Give a transistor-level circuit schematic and sketch a stick diagram for a Problem 11 Assume a CMOS inverter designed in the ON 0.5u CMOS process drives. Complementary MOSFET (CMOS) technology is widely used today to form circuits in numerous The circuit diagram of the CMOS inverter is shown in figure (4). 2.2 Charging and Discharging in CMOS Inverter...... 16. 2.3 Energy Recovery 5.31 Circuit ...

In this study, a three-dimensional ''atomistic " coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal–oxide–semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are fu...

Defuzzifier circuit is one of the most important parts of fuzzy logic controllers that determine the output accuracy. The Center Of Gravity method (COG) is one of the most accurate methods that so far been presented for defuzzification. In this paper, a simple algorithm is presented to generate triangular output membership functions in the Mamdani method using the multiplier/divider circuit and...