This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a coprocessor to reduce it by more than an order of magnitude. The coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency with a multiplication-free, non-stalling, fully pipelined architecture with modest hardware ...

The use of a centralised planning scheduler in fieldbus-based systems requiring real-time operation has proved to be a good compromise between operational flexibility and timeliness guarantees. It is particularly well adapted to embedded systems based on low-processing power microcontrollers due to the low overhead it imposes. In this paper a preliminary implementation of a hardware scheduling ...

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit sof...

Following paper examines hardware implementation methods regarding Advanced Encryption Standard (AES). Compared to software implementation, migrating to hardware provides higher level of security and faster encryption speed. An overview of existing AES hardware implementation techniques are summarized. Then the direction of reconfigurable coprocessor as a cryptography hardware is proposed. Keyw...

In this paper we present a system for accelerating special kinds of neural networks. It is a hardware supported system consisting of diierent parts. A special-purpose neural coprocessor is connected to a personal computer (PC) by a special, asynchronous interface. Two diierent neural coprocessors are available, KO-KOS, a coprocessor for Kohonen's selforganizing map, and KOBOLD, accelerating bac...

This paper presents the low power architecture of CalmRISC, a low power 8-bit microcontroller consuming only 0.1mW per MIPS at 3.0V, and its efficient coprocessor interface. The architectural consideration of CalmRISC for low power consumption is presented. Some low power circuit design schemes as well as an efficient coprocessor interface scheme in CalmRISC are proposed

This thesis is at the crossroad between Natural Language Processing (NLP) and digital circuit design. It aims at delivering a custom hardware coprocessor for accelerating natural language parsing. The coprocessor has to parse real-life natural language and is targeted to be useful in several NLP applications that are time constrained or need to process large amounts of data. More precisely, the...

A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programming and debugging of hardware ...

As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), custom instruction set extension was designed and software hardware co-design adopted; traditional pure implementation, accelerator optimization design carried out, con...