In this paper we discuss the concept of space-time diagrams as a representation of the execution of an application, and then give a method, based on critical path analysis, for calculating nontrivial upper bounds on the potential parallelism, known as the average parallelism, a complement to the speedup and efficiency.

Designing of modern digital circuits require high performance with reduced cost and minimal time to market. In order to achieve greater performance, timing analysis is done to meet all the timing constraints. It also leads to increase the complexity of emerging Very Large Scale Integration (VLSI) design. Timing analysis eliminates the occurrence of non-functional path. In this work, path tracin...

A The new global sustainability ethics 4 B. The new and emerging sustainability challenges 10 C. The new and emerging security challenges 14 D. The World Summit for Sustainable Development (WSSD) advances and retreats 19 E. The critical path forward 26

The task of finding the crisp critical path has received researcher’s attention over the past two decades which has wide range of applications in planning and scheduling the large projects. In most cases of our life, the data obtained for decision makers are only approximate, which gives rise to fuzzy critical path problem. In this paper, new ranking methods are introduced to identify the fuzzy...

Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are shown as delay faults therefore their testing is very important, mainly path delay faults. Such faults are tested over critical paths which have to be specified in a digital circuit. A problem of the critical paths selection is discus...

We present Parkour, a tool that creates parallel speedup estimates for unparallelized serial programs. Unlike previous approaches, it does not require any prior human analysis or modification of the program. Parkour automatically quantifies the parallelism of a given program and provides an approximate upper bound for performance, modeling fundamental parallelization constraints. For the evalua...

Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are id...

The ability to predict the performance of a simulationapplication before its implementation is an important factor to the adoption of parallel simulation technology in industry. Ideally, a simulationist estimates the inherent parallelism of a simulation problem to determine whether it is worthwhile to invest resources to carry out a parallel simulation. In this paper, we proposed an analytic me...

In previous reports a compile-time prediction technique has been introduced that yields lowcost, highly parameterized performance models, to be used during the initial optimization loops in parallel system design. Aimed to provide an acceptable accuracy in the face of resource contention the approach is based on a combination of asymptotic bounding analysis and critical path analysis, yielding ...