Activating a flip-flop circuit by a current fast-rising slope impulse, the circuit occupies one of the two stable states, the stable state ‘one‘ or ‘zero‘. In case of a perfect flip-flop symmetry over a large number of cycles, a noise causes the ratio of ‘ones‘ and ‘ zeros‘ is equal to one – 50% position of a flip-flop. However, any imbalance in the system changes the probability of taking a ‘o...

We present Flip-Flop Spectrum-Revealing QR (Flip-Flop SRQR) factorization, a significantly faster and more reliable variant of the QLP factorization of Stewart, for low-rank matrix approximations. Flip-Flop SRQR uses SRQR factorization to initialize a partial column pivoted QR factorization and then compute a partial LQ factorization. As observed by Stewart in his original QLP work, Flip-Flop S...

In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...

Power reduction has become a vital design goal for sophisticated design applications, whether mobile or not. dropping power consumption in design enables better, cheaper products to be designed and power-related chip failures to be minimized. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-fl...

New designs for Hybrid latch flip-flip (HLFF) and implicit-pulsed data-close-to-output (ip-DCO) flipflop circuits are proposed to improve the redundant switching activity, speed and power as these flip-flop circuits are basic building blocks of many timing elements. This paper evaluates and compares the performance of various flip-flop circuits which can reduce the effect of redundant switching...

For the first time an all optical flip-flop is demonstrated based on two coupled Mach-Zehnder interferometers which contain semiconductor optical amplifiers in their arms. The flip-flop operation is discussed and it is demonstrated using commercially available fiber pigtailed devices. Being based on Mach-Zehnder interferometers, the flip-flop has potential for very high speed operation. E-mail:...

In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional d...

Computer simulation in a single domain multilayer model is used to investigate magnetization flop in magnetic tunnel junctions, exchange-biased by pinned synthetic antiferromagnets with the multilayer structure NiFe/AlOx/Co/Ru/Co/ FeMn. The resistance to magnetization flop increases with decreasing cell size due to increased shape anisotropy and hence increased coercivity of the Co layers in th...

In this paper, a novel low power pulsed flip-flop (PFF) using self-controllable pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. In the D to Q path inverter is removed and the transistor is replaced with pass transistor logic. The pass transistor is driven by...

The paper proposed a new design for implementing a Single Edge Triggered Flip-Flop. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. In the proposed design the number of clocked transistors is reduced to decrease the power consumption and it also employs the conditional feedback to reduce the short-circuit currents. All simulations are...