We present a W-band fiber-wireless transmission system based on a nonlinear frequency multiplier for high-speed wireless short range access applications. By implementing a baseband digital signal predistortion scheme, intensive nonlinear distortions induced in a sextuple frequency multiplier can be effectively pre-compensated. Without using costly W-band components, a transmission system with 2...

This paper presents a linear multiplier that can be fully implemented in CMOS technology. The circuit implements the function of mathematical multiplication for the two input signals. Since this multiplier is not a conventional mixer, some unconventional methods were use, such as, to realize the function of multiplication, a translinear loop is implemented, which is based on the exponential rel...

Multiplier is an important block of wireless communication system. In many applications there is a need to mix the signals of different frequencies or signals of different types, which emphasises the use of mixers or multipliers for different RF applications. MOS analog multiplier with less number of transistors which can operate at ISM Band frequency with high linearity is proposed. An ISM ban...

The designing method of folded finite-impulse response (FIR) filter on pipelined array based multiplier arrays is presented in this paper. The design is considered at the bit-level of the pipelined multiplier array and internal delays are fully exploited in order to reduce power consumption and hardware complexity, transposed FIR filter forms is considered. The proposed schemes are compared as ...

We proposed a 24-GHz frequency synthesizer (FS) for automotive radar application, which consists of a phaselocked loop (PLL) and an injection-locked frequency multiplier (ILFM). Based on a novel topology, the multiply-by2 ILFM consists of a double-balanced mixer and an injectionlocked oscillator (ILO). The PLL is designed with a 12-GHz voltage-controlled oscillator (VCO) and an injection-locked...

| An 8 x 8-b nRERL serial multiplier is implemented in a 0.6m n-well 3-metal CMOS process. nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current level for ultralow-energy applications. Measurement results showed that the nRERL serial multiplier consumed only 0.9 % of the energy dissipation of the static CMOS one a...

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Quadruple, double, and single precision floating point multipliers are implemented using conventional, Canonical Signed Digit (CSD), Vedic, and radix-4 Booth multiplier methods using Verilog language and ...

We study the role of information about multiplier in a finitely repeated investment game. A high increases reputational incentives trustee, leading to more repayments. Our perfect Bayesian equilibrium analysis shows that if trustee is privately informed multiplier, both expected frequency investments and repayments as well payoffs players are higher compared situation where public knowledge. te...