A 2.4-GHz inductive degenerate differential narrowband low-noise amplifiers (LNAs) using 0.18um CMOS Technology are presented in this paper. The LNA is properly biased operates at 1.8 volts power supply and perfectly matched input impudence of 50 ohms. The LNA has the Noise figure <2.5dB, Gain(S21) >20dB,Input impedance (S11) <-20dB, Output impedance (S22) <-10dB,IIP3>-10dBm.

This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.

Active mixers operating at 23 GHz are designed and fabricated in SiGe technology. An integrated diode linearizer is used to improve the linearity of the mixer. Measurement and simulation show excellent agreement. Typically, 10 dB double-sideband noise figure, 10 dBm IIP3 and 2 dB conversion gain are measured, featuring low noise and high linearity in a same design.

This paper presents a 2.14GHz RF front end for Wide-band Code Division Multiple Access (WCDMA) receiver. The receiver is based on direct conversion architecture and implements a low noise amplifier (LNA) and a quadrature mixer in 0.25μm CMOS process. The receiver achieves a noise figure (NF) of 8.93dB, provides a gain of 17.14dB, has an IIP3 of -15.04dB and dissipate 72.15mW at 2.5V.

Yarı iletken yükselteçlerdeki bozulma, esas olarak aktif cihazların giriş-çıkış özelliklerinde karşılaşılan yüksek dereceli katsayılardan kaynaklanmaktadır. Bipolar jonksiyonlu transistörler (BJT), bir üstel diyot akım-gerilim ilişkisi ile modellendiğinde, polarlama akımından ve diğer BJT parametrelerinden bağımsız olarak, 7.33 dBm'lik giriş üçüncü dereceden intermodülasyon ürünü (IIP3) üzerind...

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giv...

A 0.18 μm CMOS low noise amplifier using RCfeedback topology is proposed with optimized matching, gain, noise, linearity and area for UWB applications. The IC prototype achieved 9.5 dB of average power gain, low 3.4 dB noise figure (NF), -9.2 dB input match, -13.5 dB return loss, -6 dBm of IIP3 and only 0.54 mm size with 15 mW power consumption. Good agreement between the simulated and measured...

A wideband CMOS variable gain low noise amplifier suitable for multi-standard radio applications between 75 MHz and 3 GHz is presented. Wideband matching to 50 Ohm (single ended) is achieved using a common-drain feedback stage whereas variable gain is realized using a resistive attenuator. The circuit has been designed in a 65 nm CMOS process and achieves 22 dB maximum gain, 29 dB gain range, 3...

A harmonic mixer for direct-conversion receivers is proposed and fabricated in a CMOS process. It is immune from both the flicker noise and self-mixing induced DC offset. Using the lateral bipolar transistor and the harmonic mixing technique, it achieves +15dB gain, 17.8dB NF at 10kHz frequency, 8.2dBm IIP3, +44dBm IIP2 and more than 30dB DC offset suppression. It consumes 2.2mW power at 3V.