In high-speed network switches and routers, packet memories have to allow line-speed buffering of data packets. With today’s growing network line-rates, memory bandwidth is an essential constraint to build high-speed network buffers. In this paper, we propose a methodology for designing high-performance network-specific memories using slower lower-cost building blocks. We use parallel memory de...

In this paper, conventional main memory and disk storage layers are merged into a single memory layer using a combination of PRAM and NAND Flash memories, which is called as an integrated memory-disk (IM-D) non-volatile memory structure. The IM-D memory architecture consists of a dual buffering IM-D adapter, an array of SLC/MLC PRAM/Flash hybrid IM-D memory, and an associated memory management ...

The increasing complexity of present SoCs demands new, scalable, reusable, parallel interconnection models for their cores. This paper presents a comparison study made in an on chip reconfigurable multiprocessor, the X4CP32, on its interconnection. Three models were proposed, a bus system, a SoC using FIFO buffering, and a SoC using SAFC buffering. All the models were described in SystemC and s...

The problem of reassembling an object from its parts or fragments has never been addressed with a unified computational approach, which depends on the pure geometric form of the parts and not application-specific features. We propose a method for the automatic reconstruction of a model based on the geometry of its parts, which may be computergenerated models or range-scanned models. The matchin...

Apparently, the buffering concept and the associated terminology are applicable if and only if the system under study has been structured in a particular way. Namely, the elements of a whole must be grouped into exactly two separate groups both of which can be condensed into a single function of a common variable. In the axiomatic definition of the signed probability measure t and the other thr...

The on-chip network (NoC) is a fundamental component of Non Uniform Cache Architectures and may significantly affect the performance of the overall system. The analysis described in this work evaluates the performance sensitivity of a single processor system adopting a NUCA L2 cache with respect to some NoC parameters, namely the hop latency and the buffering capacity of routers. The results sh...

Data copying can be a bottleneck in end-to-end communication over high-speed networks. Emulated copy is an alternative I/O data passing scheme that preserves the API and integrity guarantees of copying but avoids the latter using VM manipulations – transient output copy-on-write (TCOW), input alignment, and page swapping. We characterize and evaluate the support necessary in network adapters fo...

The existing buffers algorithms cannot effectively to meet the demands of high accuracy buffer analysis in practice although many efforts have been made past 60 years. A generalized buffering algorithm (GBA) is presented, which considers geometric distance and attribute characteristics all instances within zone. proposed includes three major steps: (1) select initialize target instance; (2) det...