This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor resides in the configurable logic, it can execute common genetic operators like crossover and mutation with a targeted data throughput of 420 MByte/s. Together with the microprocessor core, a complex evolutionary algor...

We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to ngerprint matching using Splash 2-an attached processor for SUN SPARCstation hosts. Each of the eld programmable gate array (FPGA)-based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is veriied. The nal cont...

We propose a superscalar coprocessor for high-speed curvebased cryptography. It accelerates scalar multiplication by exploiting instruction-level parallelism (ILP) dynamically and processing multiple instructions in parallel. The system-level architecture is designed so that the coprocessor can fully utilize the superscalar feature. The implementation results show that scalar multiplication of ...

* Technical University of Košice, Department of Electronics and Multimedia Communications, Park Komenského 13, 04120 Košice, Slovak Republic, E-mail: [email protected], Tel: ++421-55-6024169 , Fax: ++421-55-6323989 ** Laboratoire Traitement du Signal et Instrumentation, Unité Mixte de Recherche CNRS 5516, Université Jean Monnet, Saint-Etienne, France, E-mail: [email protected] ...

Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms are developed using a Mathematics...

“C-Level” Programming of Parallel Coprocessor Accelerators

FPGAs are an attractive platform for elliptic curve cryptography hardware. Since field multiplication is the most critical operation in elliptic curve cryptography, we have studied how efficient several field multipliers can be mapped to lookup table based FPGAs. Furthermore we have compared different curve coordinate representations with respect to the number of required field operations, and ...

The CryptoBooster is a modular and recon gurable cryptographic coprocessor that takes full advantage of current high-performance recon gurable circuits (FPGAs) and their partial recon gurability. The CryptoBooster works as a coprocessor with a host system in order to accelerate cryptographic operations. A series of cryptographic modules for di erent encryption algorithms are planned. The rst mo...

Significant investigation has taken place in the area of exploiting reconfigurable logic as a coprocessor in embedded and high-performance computer systems. This paper examines the problem of delivering high throughput data to the co-processor. Data is retrieved from magnetic storage and delivered to the coprocessor through datapaths available in inexpensive, commodity server platforms. Endto-e...