A system level fault injection experiment measuring changes in probability of failure and error propagation as a function of failure acceleration. It demonstrates that: (1) Probability of failure increases with failure acceleration, and (2) Error propagation decreases with failure acceleration .

The increasing complexity of processors allied to the continuous technology shrink is making multicore-based systems more susceptible to soft errors. The high cost and time inherent to hardware-based fault injection approaches make the more efficient simulation-based fault injection frameworks crucial to test reliability. This paper proposes a fast, flexible fault injector framework which suppo...

This paper deals with different software based strategies allowing the on-line detection of bit flip errors arising in microprocessor-based digital architectures as the consequence of the interaction with radiation. Fault injection experiments put in evidence the detection capabilities and the limitations of each of the studied techniques. RELATED TOPICS: Radiation effects, fault tolerant syste...

As the capacity of caches increases dramatically with new processors, soft errors originating in cache memories has become a major reliability concern for high performance processors. This paper presents application specific soft error vulnerability analysis in order to understand an application’s responses to soft errors from different levels of caches. Based on a high-performance processor si...

This paper introduces a new methodology for validation of dependable systems based on physical fault injection. The approach defines the elements of the injection environment and the requirements that are necessary to control the injection process with fine granularity, allowing for the elimination of glitches and not valid experiments and therefore making the validation process more accurate. ...

Technology and voltage scaling is making integrated circuits increasingly susceptible to failures caused by soft errors. The source of soft errors are temporary hardware faults that alter data and signals in digital circuits. Soft errors are predominately caused by ionizing particles, electrical noise and wear-out effects, but may also occur as a result of marginal circuit designs and manufactu...

We present a fast parallel simulator to evaluate the impact of different error control methods on the performance of networks-on-chip (NoCs). The simulator, implemented with message passing interface (MPI) language to exploit multiprocessor server environments, models characteristics of intellectual property (IP) cores, network interfaces (NIs), and routers. Moreover, different error control sc...

ÐIntel Corporation developed the Teraflops supercomputer for the US Department of Energy (DOE) as part of the Accelerated Strategic Computing Initiative (ASCI). This is the most powerful computing machine available today, performing over two trillion floating point operations per second with the aid of more than 9,000 Intel processors. The Teraflops machine employs complex hardware and software...