This paper presents an implementation of Universal Asynchronous Receiver-Transmitter (UART) controller based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our design of UART is fully functional and synthesizable. It is coded using Verilog based top-down hierarchical design methodology and realized in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. The implementation resul...

This paper discusses design and testing of a Moving Picture Experts Group 2 (MPEG-2) Transport Stream (TS) multiplexer in Field Programmable Gate Array (FPGA) technology that would transmit multiplexed packets via Ethernet. Multiplexer is designed in accordance with standard ISO/ IEC 13818-1, thus it is fully compatible with standard players. The digital design is very flexible since adding add...

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central f...

Today, real-time processing has become a stipulation in all practical fields especially in image processing. This paper presents an experimental comparison of implementation of Niblack’s Algorithm, a binarization algorithm for image-processing in Visual C++ using OpenCV library with its implementation on FPGA. It aims at addressing the real-time processing scenario and how to overcome the situa...

in the last few years, the electronic devices production field has witness a great revolution by having the new birth of the extraordinary FPGA (Field Programmable Gate Array) family platforms. These platforms are the optimum and best choice for the modern digital systems now a day. The parallel structure of a neural network makes it potentially fast for the computation of certain tasks. The sa...

Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a field-programmable gate array impleme...

Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin...

The current network technologies and market are pushing the envelope for high-performance computing power at the edge of the network. One such technology support for this computational power is the on-the-field reconfigurable technologies. In this paper we present an overview of a highly-parallel Field Programmable Gate Array (FPGA) system architecture called Super Reconfigurable Fabric Archite...

Every user of programmable logic at some point faces the question: “How large a device will I require to fit my design?” In an effort to provide guidance to their users, Field Programmable Gate Array (FPGA) manufacturers, including Xilinx, describe the capacity of FPGA devices in terms of “gate counts.” “Gate counting” involves measuring logic capacity in terms of the number of 2-input NAND gat...

The evolution of today's application technologies requires a certain level of robustness, reliability and ease of integration. We choose the Fields Programmable Gate Array (FPGA) hardware description language to implement the facial recognition algorithm based on "Eigen faces" using Principal Component Analysis. In this paper, we first present an overview of the PCA used for facial recognition,...