-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...

In this paper, a high-speed double-edge-triggered flip-flop designed in 0.18μm CMOS technology is presented. Flip-flops, to a large extend, determine the speed of synchronous systems. The proposed flip-flop can operate with a clock rate as high as 12.5GHz, which translates to 25GB/s data rate. It samples the data on both edges of the clock. All signals are realized differentially. The different...

The latches are simple circuits with feedback from the digital electrical engineering. We have included in our work the C element of Muller, the RS latch, the clocked RS latch, the D latch and also circuits containing two interconnected latches: the edge triggered RS flip-flop, the D flip-flop, the JK flip-flop, the T flip-flop. The purpose of this study is to model with equations the previous ...

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we describe the new Threshold Logic flipflop concept and circuit operation. Second, we present the concepts of embedded Threshold logic and run-time reprogrammability. Finally, it is proved by Spice simulation results that wide (up to 8 inputs) AND/OR Boolean functions can be embedded ...

In this paper, we examine the problems in the CDN of the flip flop & design an improved CDN oriented Flip-flop which is Clocked Pair Shared Flip Flop (CPSFF). Clock Division Network (CDN)’S plays an important role in the flip flop design and it’s the major element in the flip –flop for producing the logical outputs it’s much important to design the CDN with low power and area. Power consumption...

Delay faults are frequently encountered in nanometer technologies. Therefore, it is critical to detect these faults during factory test. Testing for a delay fault requires the application of a pair of test vectors in an at-speed manner. To maximize the delay fault detection capability, it is desired that the vectors in this pair are independent. Independent vector pairs cannot always be applied...

-In many digital Very Large Scale Integration design, clock system is one of the most power consumption component. It consumes 30% to 60% of the total system power. As we are in need to reduce the power consumption on portable digital circuit because power budget is severely limited on portable digital circuit. To achieve this requirement, a clock system employing two techniques such as Dual Ed...

Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show ...

Abstract An improved design of a sense amplifier-based flip-flop is presented. The new design overcomes the problems of floating nodes, which is a weakness of previously reported solutions. This is achieved by systematic derivation of flip-flop equations and rearranging the resulting network. The resulting flip-flop outperforms earlier published structures, exhibiting TCQ of 190ps when driving ...

The register element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of register ...