The plant-pathogen interaction is a multifactor process that may lead to resistance or susceptible responses of plant to pathogens. During the arms race between plant and pathogens, various biochemical, molecular and physiological events are triggered in plant cells such as ROS signaling, hormone activation and gene expression reprogramming. In plants, microRNAs (miRNAs) are key post-transcript...

Using the simple ETAS branching model of seismicity, which assumes that each earthquake can trigger other earthquakes, we quantify the role played by the cascade of triggered seismicity in controlling the rate of aftershock decay as well as the overall level of seismicity in the presence of a constant external seismicity source. We show that, in this model, the fraction of earthquakes in the po...

The formal speciication of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more diicult. However, the beneets of such a speciication can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and...

A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the array simplifies the access of the processing elements for data manipulations. The DPSS allows automatic mapping of high level datapath structures onto the rDPA without manual interaction. Optimization techniques are sketc...

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84 V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improveme...

Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput. In this paper we evaluate the suitability of Transport Trigge...

The formal speciication of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more diicult. However, the beneets of such a speciication can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and...

Abstract We formalize the correctness of a real-time scheduler in a time-triggered architecture. Where previous research elaborated on real-time protocol correctness, we extend this work to gate-level hardware. This requires a sophisticated analysis of analog bit-level synchronization and message transmission. Our case-study is a concrete automotive bus controller (ABC). For a set of interconne...

The formal speciication of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more diicult. However, the beneets of such a speciication can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and...