We have presented a behavioral to structural translator that utilizes the V erilog HDL for output. The translator produces a netlist in GRM form ooering the many advantages present in this class of circuits such as ease of testability and a reduced logic gate count. The tool is constructed in a modular manner so that other synthesis functions may be used as they become available. The mathematic...

Surface micromachined structures are composed of atomic elements like anchors, beams and fingers, which can be further grouped into components like springs, comb drives and plates. Automatic recognition of these elements and components is crucial for a structured design methodology in MEMS (Microelectromechanical system). As MEMS design tends to be layout-centric, design evaluation requires ext...

Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netl...

Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after synthesis tools embed semantic i...

ion Levels 3 Behavior (Function) Structure (Netlist) Physical (Layout) Logic Circuit Processor System

We propose a new way of decomposing completely or incompletely specified Boolean functions into a set of unate functional blocks to obtain a good initial structure for logic synthesis. The input to our algorithm is a flattened netlist. The output is a multi-level netlist that can be efficiently implemented using a logic synthesis tool. Experimental results on Espresso PLA benchmarks employing a...

This application note describes how to alter the printed wiring board (PWB) netlist of a design containing the DS33R41 Inverse-Multiplexing Ethernet Mapper with Integrated Quad Port T1/E1/J1 Transceiver so that the netlist complies with the Joint Test Action Group (JTAG) specifications. These changes are necessary because the DS33R41 was designed as a multichip module with multiple die in a sin...

A method for visualization of analog circuit schematic starting from a netlist is described in this paper. The images obtained have a comprehensible form, symmetrical structures and other analog topological patterns being discovered in the circuit netlist. The method is based on two algorithms. The first one, the symmetry algorithm, exploits the possibility to extract topology information from ...