This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. ...

An all-digital fractional-N Phase-Locked Loop (PLL) built with standard cells and digital synthesis tools allows easier integration with digital blocks and portability to different processes or technologies. This paper presents a PLL built with standard cells and digital synthesis tools and achieves good jitter performance. It uses an embedded time-to-digital converter (TDC) with multipath to i...

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the pha...

We consider the design of kernels for time-frequency distributions through the phase, rather than amplitude, response. While phase kernels do not attenuate troublesome crosscomponents, they can translate them in the time-frequency plane. In contrast to previous work on phase kernels that concentrated on placing the cross-components on top of the auto-components, we set up a “don’t care” region ...

This report summarizes a software de…ned phase locked loop and its connection to standard second-order loop design parameter for a integrating VCO and DDFS frequency synthesizer. 1 Introduction Phase locked loops (PLLs) have been used since the early development of radio. Critical paper collections [1] and books [2] cover the subject matter, which includes nonlinear feedback and stochastic di¤e...

approved: _____________________________________________________ Un-Ku Moon Kartikeya Mayaram Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This...

Phase-locked loops (PLL) are widely used in the synchronization of grid interfaced power converters. One solution is based on orthogonal signal generation (OSG), which requires frequency information for their appropriate operation. This article developed a new to achieve PLL function single-phase interconnection but eradicate additional feedback traditional architecture all-pass filter (APF-PLL...