In this paper a new 8-bit 50-Msample/s CMOS digital-to-analog converter (DAC) is presented. The circuit employs 9 operational transconductance amplifiers (OTAs) and CMOS transistors as switching circuit. The proposed DAC is simulated using SPICE simulation program with 3μm CMOS technology. Simulation results shows verify good performance of the circuit.

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal–oxide–semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAM’s), dynamic random access memories (DRAM’s), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting ...

As the minimum dimensions of CMOS transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the 'idle' power consumption of CMOS memory arrays (e.g. SRAM). This limits a number of applications, especially for FPGA circuit as its configuration da...

The Integrated Circuit Technology(IC) is growing day by day to improve circuit performance. Quantum dot cellular automata (QCA) is one of the noval technology in nano electronics, introduced to overcome the scaling limitations takes place in CMOS Technology. This technology is suitable for development of ultra-dense low-power high-performance digital circuits. In this paper we are implementing ...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

The switched-current (SI) circuit is a circuit technique which is able to realize analog sampled-data circuits with a standard CMOS technology. Among all the basic SI circuits, the memory cell circuit is the most primitive element. In this work, a practical SI memory cell which employs negative feedback circuitry and glitch reduction technique is first presented. Based on this basic cell, a uni...

A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurr...

In this paper we discuss an application of CMOS photo-sensor array chip using pulse frequency modulation (PFM) to sub-retinal implantation to recover human vision. PFM with integration mode as photo-sensing circuit is used to realize enough dynamic range and compatibility with signals in real retina. To effectively stimulate the retinal cells, we have designed a PFM circuit with limited bandwid...

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCRbased) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage...