it has been well - established that common atrial flutter is due to intraatrial macroreentry and its reentry circuit locates in the right atrium. this reentry circuit has been characterized to involve an area of slow conduction identifiable electrophysiologically at the low posteroseptal right atrium and anatomical narrow isthmus snrrounded by the inferior vena capa, coronary sinus astium and t...

Circuit-level implementation of a novel neuron has been discussed in this article. A low-power Activation Function (AF) circuit is introduced in this paper, which is then combined with a highly linear synapse circuit to form the neuron architecture. Designed in Carbon Nanotube Field-Effect Transistor (CNTFET) technology, the proposed structure consumes low power, which makes it suitable for the...

Various synthesis methods have been proposed in the literature for reversible and quantum logic circuits. However, there are few algorithms to optimize an existing circuit with multiple constraints simultaneously. In this paper, some heuristics in genetic algorithms (GA) to optimize a given circuit in terms of quantum cost, number of gates, location of garbage outputs, and delay, are proposed. ...

Abstract— In this paper, input impedance of a vertical rod under lightning stroke is first computed by applying the method of moments (MoM) on the Maxwell’s equations. The circuit model is then achieved through applying modified vector fitting (MVF) on the computed input impedance. After then the equivalent circuit is again extracted for a few values of soil conductivity and rod radius. Finally...

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.