In this paper, an FPGA-based convolutional neural network coprocessor is proposed. The has a 1D computation unit PE in row stationary (RS) streaming mode and 3D chain pulsating array structure. can flexibly control the number of openings according to output channels layer. we design storage system with multilevel cache, global cache uses multiple broadcasts distribute data local caches propose ...

Since the introduction of pairings over (hyper)elliptic curves in constructive cryptographic applications, an ever increasing number of protocols based on pairings have appeared in the literature. Software implementations being rather slow, the study of hardware architectures became an active research area. Beuchat et al. proposed for instance a coprocessor which computes the characteristic thr...

Relational database management systems can be used as a coprocessor for general-purpose programming languages, especially for those program fragments that carry out data-intensive and data-parallel computations. In this paper we present a Haskell library for databasesupported program execution. Data-intensive and data-parallel computations are expressed using familiar combinators from the stand...

One of the most critical resource management issues using TCAM for packet classification is how to effectively support rules with ranges, known as range matching. Since in general, multiple TCAM entries have to be allocated to represent a rule with ranges, it raises the question about whether TCAM can effectively support range matching. In this paper, an efficient range encoding scheme is intro...

We describe a method for speeding up divide-andconquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the “divide” and “merge” phases, while the “conquer” phase is handled by a purpose-built coprocessor. It is shown how transformation techniques from the Ruby language can be adopted in developing a family of systolic sorters,...

Since the introduction of pairings over (hyper)elliptic curves in constructive cryptographic applications, an ever increasing number of protocols based on pairings have appeared in the literature. Software implementations being rather slow, the study of hardware architectures became an active research area. Beuchat et al. proposed for instance a coprocessor which computes the characteristic thr...

The low-processing power microcontrollers used within typical CAN nodes, usually place tight limits on the complexity and flexibility of on-line message scheduling systems. One solution to break this barrier is to transfer the scheduling task to a hardware implementation. A traffic scheduling and schedulability analyser coprocessor is presented in this paper. The coprocessor generates message s...

The introduction of Intel R © Xeon Phi TM coprocessors opened up new possibilities in development of highly parallel applications. The familiarity and flexibility of the architecture together with compiler support integrated into the Intel C++ Composer XE allows the developers to use familiar programming paradigms and techniques, which are usually not suitable for other accelerated systems. It ...