This paper addresses the problem of optimal grasping of an object with a multi-fingered robotic hand for accomplishing a given task. The task is first demonstrated by a human operator and its force/torque requirements are captured through the usage of a sensorized tool. The grasp quality is computed through a task compatibility criterion. Grasp synthesis is then formulated as a single constrain...

Improving testability of complex designs through DFT (Design-For-Testability) has been widely investigated for several years. Designers are taking fully advantage of silicon compilers that allow a design to be synthesized given its behavioral description. However, test logic is still considered only once the logic synthesis is accomplished. This does not take fully advantage of the optimization...

SUMMARY This paper describes an optimal scheduling approach which nds the scheduling result of the minimum functional unit cost under the given timing constraint. In this method, a well-deened search space is constructed incremen-tally and traversed in a branch-and-bound manner. During the traversal, tighter lower bounds are estimated and utilized coupled with the upper bound on the optimal sol...

c 1994 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Formalisation of Multi-Precision Arithmetic for High-Level Synthesis of DSP Architectures MARC PAUWELS , GERT GOOSSENS, FRANCKY CATTHOOR, HUGO DE MAN [email protected] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Abstract. Multiple precision arithmetic is very useful to optimally trade o area and time when implementing re...

Vector field visualization techniques are subdivided into three categories: global, geometric, and feature-based techniques. We describe each category, and we present some related work and an example in each category from our own recent research. Spot Noise is a texture synthesis technique for global visualization of vector fields on 2D surfaces. Deformable surfaces is a generic technique for e...

This paper describes a genetic algorithm applied to high-level hardware synthesis, generating a register transfer level circuit from a behavioral speciication of a hardware system. High-Level synthesis consists of two combinatorial optimization problems; scheduling and allocation. It is also a multiple objective problem. Our GA solves the scheduling and allocation problems simultaneously so tha...

This paper describes a technique to use local timing constraints to drive the high-level synthesis process. First, the clock period and a preliminary multicycle scheduling of the operations are decided. Second, rescheduling and allocation of modules are performed to achieve an efficient implementation. These two tasks are both formulated as combinatorial optimization problems and are solved wit...

Recently there has been increased interest in the development of high-level architectural synthesis tools targeting power optimization. In this paper, we first present an overview of the various architecture synthesis tasks and analyze their influence on power consumption. A survey of previously proposed techniques is given, and areas of opportunity are identified. We next propose a new archite...