High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming much cheaper while wires are still expensive. Therefore, optimization efforts should focus on the wire resources. In this paper, we devise an objective function to balance the interconnect topology between routing are...

Substrate noise effects caused by the integration of a DC-DC converter into a 0.13 μm CMOS technology integrated circuit are investigated in this paper. Simulations performed using the Substrate Noise Analyst tool show strong impact of switching and power supply noise on a sensitive analog block. The dependence of substrate noise coupling on physical separation distance, floorplanning and intro...

This paper provides an overview of ULSI interconnect scaling trends and their implications for thermal, reliability and performance issues simultaneously. It shows how interconnect scaling requirements for deep sub-micron (DSM) technologies cause increasing thermal effects. The paper then examines the impact of thermal effects on both interconnect design and electromigration (EM) reliability. S...

Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originatedby simultaneousswitching noise. However, they are also more sensitive than synchronous ones to spurious signal transitions and delay variations produced by crosstalk noise. This paper addresses the pr...

For the sLHC phase I, the ATLAS detector will be upgraded by installation of an additional Pixel Detector layer. The new layer will be inserted between the B-layer of the existing pixel detector and a new smaller radius beam-pipe. This upgrade requires development of several new technologies to cope with increased radiation doses to which the apparatus will be exposed, signi cant rise of the pa...

Synchronizers play a key role in multi-clock domain systems on chip. Designing reliable synchronizers requires estimating and evaluating synchronizer parameters (resolution time constant) and (metastability window). Typically, evaluation of these parameters has been done by empirical rules of thumb or simple circuit simulations to ensure that the synchronizer MTBF is sufficiently long. This pap...

As the technology moves into deep sub-micron region, the power consumption of the integrated circuit will be more. In the current technologies, the leakage power is the major part in the total power consumption. Power gating is a technique which is used to reduce the leakage power by shutting off the idle logic blocks using sleep transistors. Different power gating methods are available now. Th...

The speed of digital circuit is one of the most restricting factors in the deep sub-micron and multigigahertz integrated circuits design. It is directly dependent on the circuit delay. Scaling down the technologies and increasing the operational frequency make the delay problems more important. This paper studies the delay in digital circuits, starting from the design process, scaling down the ...

Considered are: (i) separation of gaseous molecules different weight by the Ultra Centrifuge with application to large scale uranium enrichment fuel nuclear power plants; (ii) micron-sized particulate matter from fluids in mechanical devices which use is made inertial and centrifugal forces; (iii) mixtures fast expansion cooling such that one components forms a mist droplets are separated centr...