نتایج جستجو برای: mosfet device

تعداد نتایج: 680832  

2012
Pujarini Ghosh Rishu Chaujar Subhasis Haldar R. S Gupta Mridula Gupta

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material wo...

2013

Power MOSFET technology has developed toward higher cell density for lower on-resistance. The super-junction device utilizing charge balance theory was introduced to semiconductor industry ten years ago and it set a new benchmark in the high-voltage power MOSFET market [1] . The Super-Junction (SJ) MOSFETs enable higher power conversion efficiency. However, the extremely fast switching performa...

2013

Power MOSFET technology has developed toward higher cell density for lower on-resistance. The super-junction device utilizing charge balance theory was introduced to semiconductor industry ten years ago and it set a new benchmark in the high-voltage power MOSFET market [1] . The Super-Junction (SJ) MOSFETs enable higher power conversion efficiency. However, the extremely fast switching performa...

Journal: :Applied Physics Letters 2021

A normally-off inversion p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a nitrogen (N)-doped diamond body deposited using microwave plasma-enhanced chemical vapor deposition (MPECVD) was fabricated. The MOSFET exhibited drain current density of −1.7 mA/mm. Thus far, this value is similar to the device performance fabricated phosphorus (P)-doped n-type body. N2 used fo...

1999
Xuejue Huang Wen-Chin Lee Charles Kuo Digh Hisamoto Leland Chang Jakub Kedzierski Erik Anderson Hideki Takeuchi Yang-Kyu Choi Kazuya Asano Vivek Subramanian Tsu-Jae King Jeffrey Bokor Chenming Hu

High performance PMOSFETs with a gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. The 45 nm gate-length PMOS FinFET has an Idsat of 410 PA/Pm (or 820 PA/Pm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of t...

2002
Lihui Wang James D. Meindl

In this paper, quantum mechanical effects on nanoscale MOSFET devices are investigated through compact physical models. These models cover quantum mechanical influences on device parameters including long-channel threshold voltage shift, gate capacitance degradation, deteriorated short channel effects and sub-threshold slope. In-depth understanding of device characteristic modification brought ...

2012
Byron Ho Oscar Dubon

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2011
Deepesh Ranka Ashwani K. Rana Rakesh Kumar Yadav Devendra Giri K. Asano N. Lindert V. Subramanian M. Fujiwara T. Morooka N. Yasutake K. Ohuchi N. Aoki H. Tanimoto M. Kondo Ming-Wen Ma Chien-Hung Wu Tsung-Yu Yang Kuo-Hsing Kao Woei-Cherng Wu Shui-Jinn Wang Tien-Sheng Chao R. Tsuchiya K. Ohnishi M. Horiuchi S. Tsujikawa Y. Shimamoto N. Inada J. Yugami F. Ootsuka D. L. Kencke W. Chen H. Wang S. Mudanai Q. Ouyang A. Tasch S. K. Banerjee

As scaling down MOSFET devices degrade device performance in term of leakage current and short channel effects. To overcome the problem a newer device Silicon-on-Insulator (SOI) MOSFET has been introduced. The Fully Depleted (FD) SOI MOSFETs also suffer from short channel effects (SCE) in the sub 65 nm regime due to reduction in threshold voltage. Several investigations are going to reduce the ...

2012
Sonal Aggarwal Rajbir Singh

The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnec...

1997
R. Sekhar Narayanaswami Dennis Yee

Progress in CMOS device technology has motivated the design of high-performance analog integrated circuits in standard CMOS processes. In particular, the high speed of submicron CMOS devices make them attractive for a variety of analog applications, including data converters, switched capacitor circuits, and low noise amplifiers [1,2,16]. However, recent reports have indicated that the measured...

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