Tabu Search is a simple combinatorial optimization strategy that has been applied with great success in applications ranging from graph coloring to scheduling and space planning. This paper describes the application of the Tabu Searchh1] heuristic to the circuit partitioning problem. Results obtained indicate that in most cases Tabu Search yields netlist partitions with 10% fewer cut nets than ...

This paper presents a new method for encryption of color images based on a combination of chaotic systems, which makes the image encryption more efficient and robust. The proposed algorithm generated three series of data, ranged between 0 and 255, using a chaotic Chen system. Another Chen system was then started with different initial values, which were converted to three series of numbers from...

Register-Transfer (RT-) level netlists are said to be isomorphic if they can be made identical by relabeling RT-components. RT-netlists can be generated by architectural synthesis. In order to consider just the essential design decisions, architectural synthesis should consider only a single representative of sets of isomorphic netlists. In this paper, we are using netlist isomorphism for the v...

The need for detailed simulation of integrated circuits has received significant attention since the early stages of design automation. Given the increasing device integration, these simulations have extreme memory footprints, especially within unified memory hierarchies. This paper overcomes the infeasible memory demands of modern circuit simulators. Structural partitioning of the netlist and ...

This paper describes a new technique for extracting clock-level finite state machines (E'sMs) from transistor netkts using symbolic simulation. The transistor netlist is preprocessed to produce a gate-level representation of the netlist. Given specitications of the circuit clocking and input and output timing, simulation patterns are derived for a symbolic simulator. The result of the symbolic ...

We present a solution to the veri cation problem of high-level synthesis. The high-level synthesis system CALLAS takes as input an algorithmic speci cation, in VHDL, and produces as output an EDIF netlist. Both, the speci cation and the generated netlist can be interpreted as nite state machine descriptions. Then, in this context, the veri cation problem is reduced to proving the behavioral equ...

Field programmable gate array (FPGA) makes rapid pro-totyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectiication method for look-up table type FPGA's. Instead of changing the netlist of a circuit, we only modify functionality realized by look-up tables and keep the netlist equal so that there will be no change on th...

In recent years, the advancement of digital technology has led to an increase in data transmission on the Internet. Security of images is one of the biggest concern of many researchers. Therefore, numerous algorithms have been presented for image encryption. An efficient encryption algorithm should have high security and low search time along with high complexity.DNA encryption is one of the fa...

Introduction Maverick is a modern hierarchical netlist extractor, providing extraordinary effi ciency as well as comprehensive features and ease of use. It runs on PC under Microsoft Windows NT providing unique productivity in processing of virtually any size VLSI/ULSI designs. The extractor is fully integrated with state-of-the-art Expert Layout Editor, and represents important part of its ver...