Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In this paper, we present new precomputation architectures for both combinational and sequential logic and describe new precomputation-based logic synthesis methods...

Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for kpartition, which minimizes the circuit delay and cut size. Experimental results with MCNC benchmark circuits have shown that the delay in the circuit can be reduced by marginally in comparison with ...

VLSI (Very Large Scale Integration) circuits are basic components of today’s complex digital systems. In order to realize dependable digital systems, VLSI circuits should be highly reliable. VLSI testing plays an important role in satisfying this requirement. VLSI testing is to check whether faults exist in a circuit, and it consists of two main phases: test generation and test application. In ...

An implementation of a design for testability model for sequential circuits is presented. The jlip-jlops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complezity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are pre...

Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. We review proposition algebra [2010], an algebraic approach to propositional logic with side effects that models short-circuit evaluatio...

In deep submicrometer integrated circuit design, there is a growing need to quickly and accurately characterize the timing of large circuit blocks. Accurate timing characterization requires making available as much timing information as possible at each step of the design process. Conventional fast characterization methods typically employ topological analysis, which can be inaccurate because o...

Evolutionary algorithms (EAs) are regularly used both for the solution of scheduling problems, and for the creation of digital circuit designs. This paper describes a unified approach, which mixes the creation of a sequential circuit, with the scheduling and binding of operations. This paper describes how Finite Impulse Response Primitive Operator Filters (FIR POFs) can be created so that they ...

Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard...